Eddie Hung
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3247442bf9
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Revert "Revert "Fix omode which inserts an output if none exists (otherwise abc9 breaks)""
This reverts commit 8f0c1232d7 .
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2019-08-28 17:34:00 -07:00 |
Eddie Hung
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082a01954b
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Revert "Output "h" extension only if boxes"
This reverts commit 399ac760ff .
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2019-08-28 17:30:54 -07:00 |
Eddie Hung
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070f3ac561
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Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival
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2019-08-28 17:29:25 -07:00 |
Eddie Hung
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d46d38e4d5
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Trailing comma
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2019-08-28 17:25:54 -07:00 |
Eddie Hung
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f5b4bc847c
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Adapt to $__ICE40_CARRY_WRAPPER
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2019-08-28 17:25:05 -07:00 |
Eddie Hung
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e569f13870
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Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with"
This reverts commit 2aedee1f0e .
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2019-08-28 17:22:44 -07:00 |
Eddie Hung
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2421cb3fed
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Add arrival times for HX devices
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2019-08-28 17:21:37 -07:00 |
Eddie Hung
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e4f89e01b5
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Specify ice40 family to cells_sim.v using define
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2019-08-28 17:21:12 -07:00 |
Eddie Hung
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345a572449
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Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival
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2019-08-28 17:19:02 -07:00 |
Eddie Hung
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2aedee1f0e
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Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with
CARRY_WRAPPER in the same way since I0 and I3 could be used
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2019-08-28 17:07:36 -07:00 |
Eddie Hung
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077e9d4ada
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Update box size and timings
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2019-08-28 17:07:24 -07:00 |
Eddie Hung
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129df7184a
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Update to new $__ICE40_CARRY_WRAPPER
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2019-08-28 17:07:07 -07:00 |
Eddie Hung
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0af64df10c
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Account for D port being a constant
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2019-08-28 15:32:38 -07:00 |
Eddie Hung
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a45c09c8d1
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Account for D port being a constant
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2019-08-28 15:31:55 -07:00 |
Eddie Hung
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1b08f861b6
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Merge branch 'eddie/xilinx_srl' into xaig_arrival
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2019-08-28 15:31:48 -07:00 |
Eddie Hung
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8d820a9884
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Merge remote-tracking branch 'origin/master' into xaig_arrival
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2019-08-28 15:19:10 -07:00 |
Eddie Hung
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b8a9f73089
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Comment out *.sh used for testbenches as we have no more
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2019-08-28 12:36:20 -07:00 |
Eddie Hung
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fc727fa5c9
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Merge pull request #1334 from YosysHQ/clifford/async2synclatch
Add $dlatch support to async2sync
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2019-08-28 12:36:06 -07:00 |
Eddie Hung
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87d5d9b8c8
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Use equiv for memory and dpram
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2019-08-28 12:30:35 -07:00 |
Eddie Hung
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ebd0a1875b
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Use equiv_opt for latches
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2019-08-28 12:21:15 -07:00 |
Eddie Hung
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32eef26ee2
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Merge remote-tracking branch 'origin/clifford/async2synclatch' into Sergey/tests_ice40
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2019-08-28 12:18:32 -07:00 |
Eddie Hung
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52c4655de3
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No need to replace Q of slice since $shiftx is autoremove-d
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2019-08-28 11:06:11 -07:00 |
Eddie Hung
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9314a0a42e
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Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor
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2019-08-28 10:51:39 -07:00 |
Eddie Hung
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11e3eb1009
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More cleanup
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2019-08-28 10:19:35 -07:00 |
Eddie Hung
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86b538bd02
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More cleanup
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2019-08-28 10:11:09 -07:00 |
Eddie Hung
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c4d1bd988b
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Do not use default_params dict, hardcode default values, cleanup
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2019-08-28 10:06:40 -07:00 |
Eddie Hung
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64ea147236
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Add .gitignore
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2019-08-28 09:55:34 -07:00 |
Eddie Hung
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2f493fb465
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Use test_pmgen for xilinx_srl
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2019-08-28 09:55:09 -07:00 |
Eddie Hung
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c3e9627afe
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Always generate if no match
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2019-08-28 09:54:56 -07:00 |
Eddie Hung
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0ebe2c9831
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Rename test_pmgen arg xilinx_srl.{fixed,variable}
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2019-08-28 09:27:03 -07:00 |
Eddie Hung
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2e9e745efa
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Do not simplemap for variable test
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2019-08-28 09:26:08 -07:00 |
Eddie Hung
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975aaf190f
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Add xilinx_srl test
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2019-08-28 09:24:19 -07:00 |
Eddie Hung
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ba5d81c7f1
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Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
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2019-08-28 09:21:03 -07:00 |
David Shah
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13424352cc
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Merge pull request #1332 from YosysHQ/dave/ecp5gsr
ecp5: Add GSR and SGSR support
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2019-08-28 12:44:02 +01:00 |
Clifford Wolf
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c84fef92df
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Merge pull request #1335 from YosysHQ/clifford/paramap
Add "paramap" pass
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2019-08-28 10:35:47 +02:00 |
Clifford Wolf
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47ffbf554e
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Fix typo
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-28 10:06:42 +02:00 |
Clifford Wolf
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0fda0e821c
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Add "paramap" pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-28 10:03:27 +02:00 |
Clifford Wolf
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c499dc3e73
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Add $dlatch support to async2sync
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-28 09:45:22 +02:00 |
SergeyDegtyar
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fe58790f37
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Revert "Add tests for ecp5"
This reverts commit 2270ead09f .
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2019-08-28 09:49:58 +03:00 |
SergeyDegtyar
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2270ead09f
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Add tests for ecp5
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2019-08-28 09:47:03 +03:00 |
Clifford Wolf
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70c0cddb1e
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Merge pull request #1325 from YosysHQ/eddie/sat_init
In sat: 'x' in init attr should be ignored
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2019-08-28 00:18:14 +02:00 |
Marcin Kościelnicki
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d361f5ab79
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xilinx: Add SRLC16E primitive.
Fixes #1331.
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2019-08-27 20:27:12 +02:00 |
Eddie Hung
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eab3c1432b
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Merge pull request #1292 from YosysHQ/mwk/xilinx_bufgmap
Add clock buffer insertion pass, improve iopadmap.
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2019-08-27 10:19:27 -07:00 |
Eddie Hung
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28133432be
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Ignore all 1'bx in (* init *)
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2019-08-27 09:24:59 -07:00 |
Eddie Hung
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00387f3927
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Revert to using clean
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2019-08-27 09:24:32 -07:00 |
SergeyDegtyar
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980830f7b8
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Revert "Add tests for ecp5 architecture."
This reverts commit 134d3fea90 .
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2019-08-27 18:28:05 +03:00 |
Marcin Kościelnicki
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5fb4b12cb5
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improve clkbuf_inhibit propagation upwards through hierarchy
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2019-08-27 17:26:47 +02:00 |
SergeyDegtyar
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134d3fea90
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Add tests for ecp5 architecture.
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2019-08-27 18:12:18 +03:00 |
David Shah
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fc001b4731
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ecp5: Add GSR support
Signed-off-by: David Shah <dave@ds0.me>
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2019-08-27 13:07:06 +01:00 |
SergeyDegtyar
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aad9bad326
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Add tests for macc and rom;
Test cases from
https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071;
In both cases synthesized only LUTs and DFFs.
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2019-08-27 13:56:26 +03:00 |