Use rtds-action instead of yosys-cmd-ref repo.
Add rtds_action to docs configuration.
Add `.readthedocs.yaml`.
Update `DOCS_USAGE_` make target to be able to use pre-generated executables without forcing a remake.
If building from read the docs, and the current build is "latest", add `-dev` to the version string.
Requires `YOSYS_VER` to be exported by .readthedocs.yaml.
`config-clang` is the default, and doesn't need to be run first. Previous instructions were ambiguous about that point.
Add note on using a different `CXX`.
- Use `:file:` role for file names, as well as `:makevar:` and `:program:`.
- Remove deprecated `linux-arm` and `linux-riscv64` oss-cad-suite targets.
- Add link to ABC.
- More (and better) links to code examples. Formatted `:file:` text with link
to source on github.
- Includes a few extra todos (mostly picking up inline code blocks and a couple
intro reminders).
- Fixing a few missing `:yoscrypt:` and `:cmd:ref:` tags.
- Reflowing some paragraphs for spacing/width.
Highlighting the difference between `select prod %ci` and `select prod %ci2` by
introducing `sumproud.out` using the `dump` command.
Playing around with advanced cone example code.
- Filling out index descriptions for `using_yosys` and `using_yosys/synthesis`.
- To discourage skipping over these index pages, the toctree in
`using_yosys/index` is hidden and instead has inline links to the two
subsections.
- Tidying todos.
- Moves technology mapping to `techmap_synth`, leaving the techmap by example in
the internals section. `yosys_flows` gets split up, with the coarse-grain
intro replaced by `synthesis/index`, the extract pass moving to
`synthesis/extract` and model checking to `more_scripting/model_checking`.
Also adds `docs/tests/macro_commands.py` which checks all commands in
`code_examples/macro_commands` against the current yosys build. Format similar
to `run-test.sh` files: logging the file under test and reporting errors.
Adds two new `show` commands to `fifo.ys` for demo purposes.
Mention referencing named selections with `@<name>`.
Also adds a note to `example_synth` to point to the show intro.
Now comes *after* example_synth, with references back to it.
Includes some minor adjustment to the `fifo.ys` script to better demonstrate the `select` command.
Still needs an updated section on `show`.
Also includes some other minor updates.
Replace leftover `opt` example source/images with examples specific to the `opt_*` pass.
Currently has images for `opt_expr`, `opt_merge`, `opt_muxtree`, and `opt_share`.
Also includes some other TODO updates.
More `literalinclude` and references to source.
Adding `example_show.ys` and `example_lscd.ys`.
Rename `example_00` et al to `example_first` et al.
Also some other minor tidying.
Working on `opt.rst`.
Replace the hardcoded `opt` psuedo code listing with a `literalinclude` from `/cmd/opt.rst`.
Reorder and update `opt_*` list to match current `opt`.
Expand sub-section titles with the function of the pass (keeping the `:cmd:ref:` part at the end to prevent the Esbonio error in vscode when a heading starts with a directive).
Move comments about `clean` and `;;` being aliases into final `opt` subsection.
Also renames `Test suites` -> `Testing Yosys`.
Adds note on `+/`.
Clarifies that we can't entirely skip loading `cells_sim.v`, and then mentions it again later once we need it.
More on final steps (and synthesis outputs).
Filling out the hardware mapping sections, and actually highlighting the changes in schematics instead of just the memory block.
Also includes Part 4 of the coarse-grain rep, looking at `memory_collect` and putting the `synth_ice40 -top fifo -run :map_ram` command in its own (sub)section.
Includes a `no_rw_check` section label in `memory.rst` for reference (because I can't remember how to reference by heading).
Not sure about the opt output after map_ram section which has an open TODO, and the final steps section is also still open.
Split hardware mapping from `fifo.ys` into `fifo_map.ys`. Reduces size of `fifo.out` log and allows separate yosys calls in the makefile.
Some tidy up and minor changes in `fifo.ys` for better discussion.
Filled out note on `clean` (changed from `opt_clean`) and introduced `;;`.
Highlighted `$memrd` and added a paragraph about it.
More detail on the flatten and merging of `fifo_reader` block.
Brief discussion on the changes from `$memrd` to `$memrd_v2`.
Split coarse grain representation into 4 parts, loosely: fsm/opt, other optimizations/techmap/memory_dff, DSPs, alumacc/memory -nomap.
Split hardware mapping into subsections as well: memory blocks (map_ram and map_ffram), arithmetic (map_gates), FFs (map_ffs), LUTs (map_luts and briefly abc), and other (map_cells and a note on hilomap and iopadmap).
Also add `-T` flag to Yosys call to remove footer from log output.
Added highlighting in (most) schematics.
Written down to end of coarse-grain, with a couple of TODOs for filling in gaps.
Includes `techmap_synth.rst` stub.
Fifo code based on SBY quick start.
Instead of showing the full design we are (currently) focusing on a single output (rdata), using `%ci*` to get the subcircuit it relies on.
Overall structure in place to match the iCE40 flow.
Still needs a new example design, and more text for the later sections (which the counter doesn't cover).
Updates code examples, removing `counter_outputs.ys` in favour of a single script. Also adds a .gitignore for the output file `synth.v`.
`example_synth.rst` still pending updated example.
Moved the last files out of the resources directory.
Some tidy up/reformatting of the extensions to allow literalincludes from `my_cmd.cc`.
Most (all?) of the getting started guidelines file is either in the quick guide section, or sections referenced by it. Instead of including it verbatim, we'll instead just leave a reference to it but then jump straight into the quick guide.
Include an image for the absval generated module. Still needs more surrounding text but it's good enough for now.
Also includes some other minor tidying, including removing the no longer used abc_01 code example.
Includes comparison of `abc` v `abc9`. Also creates a new subsection of the
yosys internals for extending yosys (moving the previous extensions.rst into it).
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
Blocking tasks are now capital TODO (compared to non-blocking todo).
Updated some of the todos.
Added note about which intel synth does which families.
Rename extended Yosys universe to Yosys family.
Added brief text to landing page, and also a note about the restructure and where to find old docs.
Moved todolist above ToC in preparation for disabling it in the config (so that it doesn't need it's own header).
Fixed pdf build, was previously breaking on trying to include the svg badges.
Includes CAD suite info and details on the OSS CAD suite nightly build targets.
Instructions for building from source, largely based on the readme but with some minor modifications.
Tests are still WIP, but we replaced the old test suites with a brief comment on the github workflow tests. Still needs more on the tests themselves and how to run them locally.
Also an extra todo on the index page.
Based on the Ignite presentation and github.
Adds links for the extended Yosys universe.
Moves the original thesis stuff further down (and labels it as such).
Moved remaining content into relevant places.
Added `load_design.rst` to more scripting.
Split fsm handling and abc out of optimization passes. Also moved things around to match the general flow previously described.
Changed generic `synth` for `prep` instead.
Replace `typical_phases.rst` and `examples.rst` with a single `example_synth.rst`.
Also updating the counter example to match.
Aims to reduce redundancy, and simplify the getting started section.
Details on things like `proc`, `memory` and `fsm` should instead be in the advanced section (under the new `synth` subsection).
Krystine Sherwin
Miodrag Milanovic
Emil J
James Meech
Emil J. Tywoniak
Martin Povišer
Rui Chen
passingglance
Catherine