7 Commits

Author	SHA1	Message	Date
Dan Ravensloft	85a14895ca	synth_intel: a10gx -> arria10gx	2019-12-10 13:48:10 +00:00
Dan Ravensloft	eab3272cde	synth_intel: cyclone10 -> cyclone10lp	2019-12-10 13:47:58 +00:00
Ben Widawsky	7de098ad45	techlibs/intel: Clean up Makefile ... Use GNU make's foreach iterator and remove nonexistent files. Gmake is already a requirement of the build system. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>	2019-08-05 11:22:11 -07:00
Dan Ravensloft	67b4ce06e0	intel: Map M9K BRAM only on families that have it ... This regresses Cyclone V and Cyclone 10 substantially, but these numbers were artificial, targeting a BRAM that they did not contain. Amusingly, synth_intel still does better when synthesizing PicoSoC than Quartus when neither are inferring block RAM.	2019-07-23 18:11:11 +01:00
dh73	3fd1d61e2a	Initial Cyclone 10 support	2017-11-08 22:45:21 -06:00
Larry Doolittle	50bcd9a728	Clean whitespace and permissions in techlibs/intel	2017-10-05 16:23:49 +02:00
dh73	cbaba62401	Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now	2017-10-01 11:04:17 -05:00