riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
12,913 Commits 92 Branches 49 Tags 39 MiB
Commit Graph

12913 Commits

Author SHA1 Message Date
Charlotte 2d7b8f71cc docs: first pass $print documentation 2023-08-11 04:46:52 +02:00
Charlotte 289f8d42cb fmt: correct parsing of {{ and }} for brace literals 2023-08-11 04:46:52 +02:00
Charlotte 3c8f84b70b fmt: fix another overrun 2023-08-11 04:46:52 +02:00
Charlotte 28bd3a4b5d fmt: don't overrun fmt string buffer 
For input like "{", "{1", etc., we would exit the loop due to
`i < fmt.size()` no longer being the case, and then check if
`++i == fmt.size()`.  That would increment i to `fmt.size() + 1`,
and so execution continues.

The intention is to move i beyond the ':', so we do it only in that
case instead.
 2023-08-11 04:46:52 +02:00
Charlotte 51d9b73107 fmt: tests completing again 
We need to invoke "read_verilog" manually, since the default action on
input files is to defer processing.  Under such conditions, we never
simplify the AST, and initial $prints never execute.
 2023-08-11 04:46:52 +02:00
Charlotte 9db73aa872 celltypes: add `$print` 
Otherwise, the \TRG connection is pruned by CleanZeroWidthPass.
 2023-08-11 04:46:52 +02:00
Charlotte 1eff84cb92 fmt: ensure test exits on fail 
shebang not honoured when directly called with "bash run-test.sh".
 2023-08-11 04:46:52 +02:00
whitequark c285880684 fmt: add tests for Verilog round trip of format expressions. 2023-08-11 04:46:52 +02:00
whitequark 67052f62ec fmt: add tests for Yosys evaluation of format expressions. 2023-08-11 04:46:52 +02:00
whitequark 3f8eab15bb write_verilog: translate $print cells to $write tasks in always blocks. 2023-08-11 04:46:52 +02:00
whitequark d51ecde8c2 clean: keep $print cells, since they have unmodelled side effects. 2023-08-11 04:46:52 +02:00
whitequark d5c9953c09 ast: translate $display/$write tasks in always blocks to new $print cell. 2023-08-11 04:46:52 +02:00
whitequark 9f8e039a4b ast: use new format string helpers. 2023-08-11 04:46:52 +02:00
whitequark 9ea241711e kernel: add format string helpers, `fmt`. 2023-08-11 04:46:52 +02:00
whitequark f8e2c955fc read_verilog: set location of AST_TCALL. 
Useful for error reporting of $display() arguments, etc.
 2023-08-11 04:46:52 +02:00
Krystine Sherwin 685da6a2e5
Converting a number of inline commands to refs 
Also reflowing text for line width.
Maybe look into supporting commands with options?
 2023-08-08 12:45:47 +12:00
Krystine Sherwin f8333e52f7
cmd links use title text 2023-08-08 12:19:13 +12:00
github-actions[bot] 389b8d0f94 Bump version 2023-08-08 00:16:52 +00:00
Krystine Sherwin 9fcf353734
Makefile adjustments to match top make 
Hopefully matches enough that any `make docs` call will work from the yosys being built, while still being overridable locally.
 2023-08-08 11:53:36 +12:00
Krystine Sherwin 8203a01ba9
Adding custom domain for cmdref 2023-08-08 11:51:57 +12:00
Krystine Sherwin d8b8880ad6
Convert todo comments to directives 
Could be left in for final version, but my current thinking is not?
 2023-08-08 10:06:19 +12:00
Krystine Sherwin ce9e56db47
Move the last presentation slides 2023-08-08 09:50:36 +12:00
Miodrag Milanovic 105c447010 Next dev cycle 2023-08-07 08:25:37 +02:00
Miodrag Milanovic fbab08acf1 Release version 0.32 2023-08-07 08:22:52 +02:00
Krystine Sherwin afc25afaf9
Minor tidying 2023-08-07 12:58:52 +12:00
Krystine Sherwin 8ade2182b0
Move (most of) ExOth and ExAdv slides 2023-08-07 12:58:40 +12:00
Krystine Sherwin 7ab051778e
Add copypaste reminder for typical_phases.rst 2023-08-07 10:40:36 +12:00
github-actions[bot] e0ba07aed3 Bump version 2023-08-05 00:16:43 +00:00
Martin Povišer ff3c7873f5 wreduce: Group reconnections 
Group the reconnections, so that instead of producing

  connect $auto$wreduce.cc:455:run$24 [0] 1'0
  connect $auto$wreduce.cc:455:run$23 [31] 1'0
  connect $auto$wreduce.cc:455:run$23 [30] 1'0
  ... (40 more lines)

we produce

  connect $auto$wreduce.cc:461:run$23 [31:11] 21'000000000000000000000
  connect $auto$wreduce.cc:461:run$24 [31:10] 22'0000000000000000000000

.
 2023-08-04 14:43:59 +01:00
Miodrag Milanović 701b767736
Merge pull request #3871 from jix/smtbmc-sexpr-scan 
smtbmc: Avoid quadratic behavior when scanning s-exprs
 2023-08-04 14:47:50 +02:00
Krystine Sherwin 330a2272da
Converting PRESENTATION_ExSyn 2023-08-04 10:29:14 +12:00
Krystine Sherwin 4b40372446
Tidy/reflow some things 2023-08-03 10:37:43 +12:00
Krystine Sherwin 2c75b103d6
Include test suites doc with note 2023-08-03 09:20:30 +12:00
Krystine Sherwin 9a9aa2c45a
Finished presentation intro 
Also some other tidy up.
 2023-08-03 09:20:30 +12:00
Krystine Sherwin 20c2708383
Move presentation intro example 
Rework images makefile a bit to get it to import and build from resources folder(s).
Currently requires running twice from a clean build due to the way it finds `.dot` files to convert.
 2023-08-03 09:20:29 +12:00
Krystine Sherwin cd6e63e1a9
Moved presentation_prog 2023-08-03 09:20:29 +12:00
Krystine Sherwin 045c04096e
Reorganising documentation 
Also changing to furo theme.
 2023-08-03 09:20:29 +12:00
Krystine Sherwin 4f1cd66829
New structure headings 
Also adds a note to readme for installing pdflatex if it's missing.
 2023-08-03 09:20:24 +12:00
github-actions[bot] f37ce5c839 Bump version 2023-08-02 00:16:17 +00:00
Jannis Harder 77c7355d53 smtbmc: Avoid quadratic behavior when scanning s-exprs 
The previous implementation for finding the end of a top-level s-expr
exhibited quadratic behavior as it would re-scan the complete input for
the current expression for every new line. For large designs with
trivial properties this could easily take seconds and dominate the
runtime over the actual solving.

This change remembers the current nesting level between lines, avoiding
the re-scanning.
 2023-08-01 17:19:29 +02:00
Jannis Harder b9751ef0b0 Install yw.h and json.h 2023-08-01 13:51:04 +01:00
Martin Povišer f8325f66b7 opt_expr: Fix 'signed X>=0' replacement for wide output ports 
If the `$ge` cell we are replacing has wide output port, the upper bits
on the port should be driven to zero. That's not what a `$not` cell with
a single-bit input does. Instead opt for a `$logic_not` cell, which does
zero-pad its output.

Fixes #3867.
 2023-08-01 13:50:12 +01:00
Miodrag Milanović 8b2a3d60f4
Merge pull request #3841 from povik/test-aigmap 
tests: Extend aigmap.ys with SAT comparison
 2023-08-01 09:04:47 +02:00
github-actions[bot] 6bf6e3307c Bump version 2023-08-01 00:19:43 +00:00
Martin Povišer 93988ef5df tests: Extend aigmap.ys with SAT comparison 
Extend the aigmap.ys test with SAT-based comparison of the original
cells and their AIG implementations.

This tests both the usual cells and the single-bit Yosys gates.
 2023-07-31 16:26:50 +02:00
Jannis Harder 0a3f805daa
Merge pull request #3840 from povik/cellaigs-cmp-cells 2023-07-31 16:23:39 +02:00
Miodrag Milanović 809466c5c5
Merge pull request #3861 from YosysHQ/verific_blackbox 
Add ability to blackbox modules/units from file while reading with Verific
 2023-07-31 16:11:16 +02:00
Miodrag Milanović a43e26e3e9
Merge pull request #3865 from dragonmux/fix/rtlil-teardown-segfault 
Fix: RTLIL teardown segfault
 2023-07-31 16:10:39 +02:00
Miodrag Milanovic 19d5293657 when blackboxing no need to know missing modules 2023-07-31 09:18:54 +02:00
dragonmux ef7e358576
kernel/rtlil: Trailing whitespace cleanup 2023-07-26 20:50:55 +01:00