Clifford Wolf
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842ca2f011
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Progress on presentation
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2014-01-28 06:51:50 +01:00 |
Clifford Wolf
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a3ac6b6f47
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Progress on presentation
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2014-01-27 20:42:35 +01:00 |
Clifford Wolf
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fb4c3dff33
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Added first presentation slides
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2014-01-27 17:08:19 +01:00 |
Clifford Wolf
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fa103e55ad
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Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys
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2014-01-26 02:29:19 +01:00 |
Clifford Wolf
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fd6ca84f3c
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Merge pull request #21 from hansiglaser/master
beautified write_intersynth, enabled multiple "-map" for the extract pass
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2014-01-25 17:28:17 -08:00 |
Johann Glaser
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e9a2094774
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enabled multiple "-map" for the extract pass
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2014-01-25 21:11:34 +01:00 |
Johann Glaser
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f13b3518aa
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beautified write_intersynth
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2014-01-25 20:16:38 +01:00 |
Ahmed Irfan
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0325efe172
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root bug corrected
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2014-01-25 19:33:24 +01:00 |
Clifford Wolf
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c1ed2607fb
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Added support for // comments in liberty parser
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2014-01-25 06:32:16 +01:00 |
Clifford Wolf
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a139b49401
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Merge branch 'btor'
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2014-01-24 23:44:46 +01:00 |
Ahmed Irfan
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137742786e
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removed regex include
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2014-01-24 18:04:37 +01:00 |
Ahmed Irfan
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2e44b1b73a
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merged clifford changes + removed regex
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2014-01-24 17:35:42 +01:00 |
Clifford Wolf
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210dda286f
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Use techmap -share_map in btor scripts
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2014-01-24 15:52:16 +01:00 |
Clifford Wolf
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6804edd5d4
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Moved btor scripts to backends/btor/
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2014-01-24 15:48:07 +01:00 |
Clifford Wolf
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da26bb4378
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Restored Makefile
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2014-01-24 15:47:09 +01:00 |
Clifford Wolf
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ec167350b4
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Restored IdString::check()
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2014-01-24 15:46:41 +01:00 |
Clifford Wolf
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d8300d1fb8
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Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys into btor
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2014-01-24 15:43:42 +01:00 |
Clifford Wolf
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0b47d907d3
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Fixed handling of unsized constants in verilog frontend
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2014-01-24 15:05:24 +01:00 |
Ahmed Irfan
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761b8f99d7
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minor change in script
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2014-01-24 15:00:43 +01:00 |
Ahmed Irfan
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9d07d83c5a
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Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
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2014-01-22 10:45:21 +01:00 |
Clifford Wolf
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88fbdd4916
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Fixed algorithmic complexity of AST simplification of long expressions
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2014-01-20 20:25:20 +01:00 |
Ahmed Irfan
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aa3cb20e1e
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slice bug corrected
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2014-01-20 18:35:52 +01:00 |
Ahmed Irfan
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c347f2825f
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assert feature
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2014-01-20 10:45:02 +01:00 |
Ahmed Irfan
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b7adf4c7a0
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Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
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2014-01-20 09:58:04 +01:00 |
Clifford Wolf
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32a91458a7
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Added hilomap command
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2014-01-19 21:58:58 +01:00 |
Clifford Wolf
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03a876c7e8
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Added sat -tempinduc and sat -prove-asserts
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2014-01-19 16:35:17 +01:00 |
Clifford Wolf
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c36bac0e10
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Added $assert support to satgen
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2014-01-19 15:37:56 +01:00 |
Clifford Wolf
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1e67099b77
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Added $assert cell
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2014-01-19 14:03:40 +01:00 |
Clifford Wolf
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9a1eb45c75
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Added Verilog parser support for asserts
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2014-01-19 04:18:22 +01:00 |
Ahmed Irfan
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234d0d0e1c
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script added
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2014-01-18 21:54:52 +01:00 |
Ahmed Irfan
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90483f489b
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Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor
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2014-01-18 19:45:16 +01:00 |
Clifford Wolf
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3d7a1491aa
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Fixed $lut simlib model for a wider range of tools
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2014-01-18 19:31:40 +01:00 |
Clifford Wolf
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13359d65ba
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Fixed parsing of verilog macros at end of line
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2014-01-18 19:22:20 +01:00 |
Clifford Wolf
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2fbaaaca7a
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More changes to simlib to make it friendlier to a wider range of tools
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2014-01-18 19:13:43 +01:00 |
Clifford Wolf
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4a9e133fab
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Fixed a type in $mem model in simlib.v
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2014-01-18 18:54:50 +01:00 |
Ahmed Irfan
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b281e13263
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Merge branch 'master' of https://github.com/ahmedirfan1983/yosys
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2014-01-18 18:11:26 +01:00 |
Ahmed Irfan
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1dd797ab09
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Merge branch 'master' of https://github.com/cliffordwolf/yosys
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2014-01-18 18:10:31 +01:00 |
Ahmed Irfan
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da8af91552
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pmux2mux
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2014-01-18 17:29:55 +01:00 |
Clifford Wolf
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bef17eeb10
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Removed cases of trailing comma in stdcells.v
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2014-01-18 15:36:17 +01:00 |
Clifford Wolf
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5b96675696
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Added $bu0 cell to simlib.v
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2014-01-18 15:35:15 +01:00 |
Clifford Wolf
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839af272ad
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Improved setundef random number generator
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2014-01-18 02:56:36 +01:00 |
Clifford Wolf
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091d9abc3e
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Added setundef command
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2014-01-17 23:14:36 +01:00 |
Clifford Wolf
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548d5aafa4
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Some improvements in log_dump_val_worker() templates
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2014-01-17 23:14:17 +01:00 |
Clifford Wolf
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db9cf544b8
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Added techlibs/common/pmux2mux.v
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2014-01-17 20:06:15 +01:00 |
Ahmed Irfan
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9a689f33a5
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verilog default options pull
shift operator width issues
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2014-01-17 19:32:35 +01:00 |
Ahmed Irfan
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fc3f2961be
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Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor
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2014-01-17 19:07:41 +01:00 |
Ahmed Irfan
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f2ee57f798
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Merge pull request #4 from cliffordwolf/master
verilog defaults
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2014-01-17 10:07:05 -08:00 |
Clifford Wolf
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6170cfe9cd
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Added verilog_defaults command
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2014-01-17 17:22:29 +01:00 |
Clifford Wolf
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2e370d5a2f
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Added support for $adff with undef data inputs to opt_rmdff
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2014-01-17 16:42:40 +01:00 |
Clifford Wolf
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651ce67d97
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Added select -assert-none and -assert-any
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2014-01-17 16:34:50 +01:00 |