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509 Commits

Author SHA1 Message Date
Eddie Hung 0895093c7c Leftover printf 2019-03-22 19:14:04 -07:00
Eddie Hung 456295eb66 Fixes for multibit 2019-03-22 18:32:42 -07:00
Eddie Hung 03d108cd1f Working for 1 bit 2019-03-22 17:46:49 -07:00
Eddie Hung 5597270b9e Opt 2019-03-21 10:20:27 -07:00
Eddie Hung 2b911e270b Fix spacing 2019-03-20 12:28:39 -07:00
Eddie Hung 505e4c2d59 Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length 2019-03-19 21:58:05 -07:00
Eddie Hung 5445cd4d00 Add support for variable length Xilinx SRL > 128 2019-03-19 17:44:33 -07:00
Eddie Hung 4cd8f02973 shregmap -tech xilinx to delete $shiftx for var length SRL 2019-03-19 15:05:08 -07:00
Eddie Hung 0ea7eba5f1 Make output port a non chain user 2019-03-19 13:08:43 -07:00
Eddie Hung ed32119d13 Fix shregmap to correctly recognise non chain users; cleanup 2019-03-18 16:12:19 -07:00
Eddie Hung b94db54664 shiftx NULL pointer check 2019-03-18 13:35:54 -07:00
Eddie Hung d6d9ef0fee Cleanup 2019-03-16 12:49:46 -07:00
Eddie Hung fadeadb8c8 Only accept <128 for variable length, only if $shiftx exclusive 2019-03-16 08:51:13 -07:00
Eddie Hung 06f8f2654a Working 2019-03-15 19:13:40 -07:00
Eddie Hung 8af9979aab Revert "Add shregmap -init_msb_first and use in synth_xilinx" 
This reverts commit 26ecbc1aee.
 2019-03-14 09:01:48 -07:00
Eddie Hung f1a8e8a480 Merge remote-tracking branch 'origin/master' into xc7srl 2019-03-14 08:59:19 -07:00
Eddie Hung 26ecbc1aee Add shregmap -init_msb_first and use in synth_xilinx 2019-03-14 08:10:02 -07:00
Eddie Hung f7c7003a19 Merge remote-tracking branch 'origin/master' into xaig 2019-02-26 13:16:03 -08:00
Eddie Hung 7cac3b1c8b abc9 -- multiple connections for inouts 2019-02-26 12:18:28 -08:00
Larry Doolittle 61fc411c5d Clean up some whitepsace outliers 2019-02-26 09:39:46 -08:00
Eddie Hung 967297cd57 abc9 cleanup 2019-02-25 18:40:53 -08:00
Eddie Hung 721f6a14fb read_aiger to accept empty string for clk_name, passable only if no latches 2019-02-25 15:34:02 -08:00
Eddie Hung 0ca3fd6a1c abc9 not to clean after aigmap 2019-02-25 15:31:52 -08:00
Eddie Hung 51f28a6747 abc9 to call "clean" once at the end of all abc9_module() calls 2019-02-25 12:55:47 -08:00
Eddie Hung d56f02d1fc abc9 to use AIGER symbol table, as opposed to map file 2019-02-21 17:03:40 -08:00
Eddie Hung 2811d66dea Revert "abc9 to write_xaiger -symbols, not -map" 
This reverts commit 04429f8152.
 2019-02-21 14:58:40 -08:00
Eddie Hung 7ad9628f07 Remove irrelevant citations 2019-02-21 14:41:11 -08:00
Eddie Hung 085ed9f487 Add attribution 2019-02-21 14:40:13 -08:00
Eddie Hung 875a02a6f2 abc9 to not select anything extra, and pop selection after final clean 2019-02-21 14:38:52 -08:00
Eddie Hung 04429f8152 abc9 to write_xaiger -symbols, not -map 2019-02-21 14:28:36 -08:00
Eddie Hung 3307295488 Merge branch 'read_aiger' into xaig 2019-02-21 14:27:32 -08:00
Eddie Hung 7f8f36273a abc9 to use &mfs 2019-02-21 13:16:24 -08:00
Eddie Hung 6b96df41bc abc9 to only disconnect output ports of AND and NOT gates 2019-02-21 11:15:47 -08:00
Eddie Hung 7f26043caf ABC -> ABC9 2019-02-20 17:36:57 -08:00
Eddie Hung e5b8bb9faa abc9 to disconnect mapped_mods POs correctly, and do not count $_NOT_ 2019-02-20 17:33:35 -08:00
Eddie Hung 32853b1f8d lut/not/and suffix to be ${lut,not,and} 2019-02-20 16:30:30 -08:00
Eddie Hung 2ca83005fb abc9 to cope with multiple modules 2019-02-20 12:56:15 -08:00
Eddie Hung d6b317b349 abc9 to use & syntax for -fast, and name fixes 2019-02-20 12:40:17 -08:00
Eddie Hung 62e5ff9ba8 abc9 to cope with indexed wires when creating $lut from $_NOT_ 2019-02-19 16:06:03 -08:00
Eddie Hung 8158bc3f99 abc9 to replace $_NOT_ with $lut 2019-02-19 12:30:20 -08:00
Eddie Hung 45d49d5d14 Get rid of debugging stuff in abc9 2019-02-16 22:25:22 -08:00
Eddie Hung f853b2f3c1 abc9 to write_aiger with -O option, and ignore dummy outputs 2019-02-16 20:09:40 -08:00
Eddie Hung d8c4d4e6c7 abc9 to handle comb loops, cope with constant outputs, disconnect using new wire 2019-02-16 13:47:38 -08:00
Eddie Hung d4545d415b abc9 to cope with non-wideports, count cells properly 2019-02-16 08:53:06 -08:00
Eddie Hung f8d0134598 Move lookup inside if 2019-02-15 15:23:26 -08:00
Eddie Hung a786ac4d53 Refactor 2019-02-15 13:00:13 -08:00
Eddie Hung 914546efd9 Cope with width != 1 when re-mapping cells 2019-02-15 12:55:52 -08:00
Eddie Hung 956ee545c5 abc9 to stitch results with CI/CO properly 2019-02-15 11:52:34 -08:00
Eddie Hung 206f11dca3 Fix stitching 2019-02-13 17:04:23 -08:00
Eddie Hung f0f5d8a5cc Merge remote-tracking branch 'origin/read_aiger' into xaig 2019-02-13 14:09:36 -08:00
Eddie Hung 87f059adf7 Rip out some more stuff 2019-02-13 10:44:52 -08:00
Eddie Hung 045f7763ae Rip out unused functions in abc9 2019-02-12 16:25:22 -08:00
Eddie Hung b3341b4abb WIP for ABC with aiger 2019-02-12 09:31:22 -08:00
Eddie Hung c23e3f0751 Missing headers for Xcode? 2019-02-12 09:24:13 -08:00
Eddie Hung 5a0a5aae4f Compile abc9 2019-02-08 13:58:47 -08:00
Eddie Hung e25a22015f Copy abc.cc to abc9.cc 2019-02-08 13:23:54 -08:00
David Shah 58c22dae31 abc: Improved recovered netnames, also preserve src on nets with dress 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-06 22:23:13 +01:00
David Shah 8524a479b1 abc: Preserve naming through ABC using 'dress' command 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-06 22:23:13 +01:00
whitequark e792bd56b7 flowmap: clean up terminology. 
* "map": group gates into LUTs;
  * "pack": replace gates with LUTs.

This is important because we have FlowMap and DF-Map, and currently
our messages are ambiguous.

Also clean up some other log messages while we're at it.
 2019-01-08 02:05:06 +00:00
whitequark 211c26a4c9 flowmap: implement depth relaxation. 2019-01-08 01:13:05 +00:00
whitequark 8b44198e23 flowmap: construct a max-volume max-flow min-cut, not just any one. 2019-01-06 19:51:37 +00:00
whitequark 2fcc1ee72e flowmap: add -minlut option, to allow postprocessing with opt_lut. 2019-01-04 21:18:03 +00:00
whitequark 9bc5cf0844 flowmap: cleanup for clarity. NFCI. 2019-01-04 13:04:20 +00:00
whitequark fd21564deb flowmap: improve debug graph output. NFC. 2019-01-04 03:30:04 +00:00
whitequark 7850a0c28a flowmap: add link to longer version of paper. NFC. 2019-01-04 02:33:10 +00:00
whitequark 07af772a72 flowmap: new techmap pass. 2019-01-03 14:28:19 +00:00
Icenowy Zheng 256fb8c95c Add "dffinit -noreinit" parameter 
Sometimes the FF cell might be initialized during the map process, e.g.
some FPGA platforms (Anlogic Eagle and Lattice ECP5 for example) has
only a "SR" pin for a FF for async reset, that resets the FF to the
initial value, which means the async reset value should be set as the
initial value. In this case the DFFINIT pass shouldn't reinitialize it
to a different value, which will lead to error.

Add a "-noreinit" parameter for the safeguard. If a FF is not
technically initialized before DFFINIT pass, the default value should be
set to x.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2018-12-18 23:10:40 +08:00
Icenowy Zheng fec8b3c81f Add "dffinit -strinit high low" 
On some platforms the string to initialize DFF might not be "high" and
"low", e.g. with Anlogic TD it's "SET" and "RESET".

Add a "-strinit" parameter for dffinit to allow specify the strings used
for high and low.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2018-12-18 15:37:43 +08:00
Clifford Wolf 2641a3089b
Revert "Proof-of-concept: preserve naming through ABC using dress" 2018-12-16 21:27:31 +01:00
Clifford Wolf 0d9c850a07
Merge pull request #735 from daveshah1/trifixes 
deminout fixes
 2018-12-16 16:02:21 +01:00
Clifford Wolf a1fb5b1e4b
Merge pull request #714 from daveshah1/abc_preserve_naming 
Proof-of-concept: preserve naming through ABC using dress
 2018-12-16 15:41:30 +01:00
David Shah 4c59447168 deminout: Consider $tribuf cells 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-12 17:17:40 +00:00
David Shah d3fe9465f3 deminout: Don't demote constant-driven inouts to inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-12 16:50:46 +00:00
David Shah 1dfb2fecab abc: Preserve naming through ABC using 'dress' command 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 15:05:07 +00:00
whitequark d1f2cb01dc lut2mux: handle 1-bit INIT constant in $lut cells. 
This pass already handles INIT constants shorter than 2^width, but
that was not done for the recursion base case.
 2018-12-05 19:27:48 +00:00
Clifford Wolf c800e3bb16 Fix typo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-04 23:30:23 +01:00
Sylvain Munaut 8d3ab626ea dff2dffe: Add option for unmap to only remove DFFE with low CE signal use 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-27 21:50:42 +01:00
Niels Moseley cfc9b9147c DFFLIBMAP: changed 'missing pin' error into a warning with additional reason/info. 2018-11-06 12:11:52 +01:00
Clifford Wolf 719e29404a Allow square brackets in liberty identifiers 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-05 12:33:33 +01:00
Niels Moseley 04cd179696 Liberty file newline handling is more relaxed. More descriptive error message 2018-11-03 18:38:49 +01:00
Niels Moseley d1e8249f9a Report an error when a liberty file contains pin references that reference non-existing pins 2018-11-03 18:07:51 +01:00
Clifford Wolf 67b1026297
Merge pull request #591 from hzeller/virtual-override 
Consistent use of 'override' for virtual methods in derived classes.
 2018-08-15 14:05:38 +02:00
Clifford Wolf 0eaab6cd1d Add missing <deque> include (MSVC build fix) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-22 15:21:59 +02:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
David Shah 459d367913 ecp5: Adding synchronous set/reset support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-14 16:18:01 +02:00
Clifford Wolf 675a44b41a Be slightly less aggressive in "deminout" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-19 14:29:38 +02:00
Robert Ou 9763e4d830 Fix infinite loop in abc command under emscripten 2018-05-18 22:42:39 -07:00
Robert Ou bfce3a7479 Add an option to statically link abc into yosys 
This is currently incomplete because the output filter no longer works.
 2018-05-18 22:35:28 -07:00
Clifford Wolf fe80b39f56 Fix iopadmap for loops between tristate IO buffers 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-15 14:02:27 +02:00
Clifford Wolf edd297fb1c Fix iopadmap for cases where IO pins already have buffers on them 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-15 13:13:43 +02:00
Clifford Wolf 145c685de0 Add ABC FAQ to "help abc" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-04 21:59:31 +02:00
Clifford Wolf a572b49538 Replace -ignore_redef with -[no]overwrite 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-03 15:25:59 +02:00
Clifford Wolf 705c366a91 Added missing dont_use handling for SR FFs to dfflibmap 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-05 11:01:45 +02:00
Clifford Wolf a74f805ba0 Fix handling of src attributes in flatten 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-10 13:55:30 +01:00
Clifford Wolf 9ac560f5d3 Add "dffinit -highlow" and fix synth_intel 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-09 18:42:19 +01:00
Clifford Wolf a96c775a73 Add support for "yosys -E" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-07 16:36:13 +01:00
Staf Verhaegen 92eb841f0a Value of properties can be expression. 
Example found in the 2007.03 Liberty Reference Manual that was also found
in the wild:

    input_voltage(CMOS) {
        vil : 0.3 * VDD ;
        vih : 0.7 * VDD ;
        vimin : -0.5 ;
        vimax : VDD + 0.5 ;
    }

Current implementation just parses the expression but no interpretation is done.
 2018-01-03 21:37:17 +00:00
Clifford Wolf 7c57d8fbb4 Rewrite ABC output to include proper net names in timing report 2017-10-10 13:32:58 +02:00
Andrew Zonenberg 2b65b65d70 Added missing "break" 2017-09-15 17:54:52 -07:00
Andrew Zonenberg 7b3966714c Implemented off-chain support for extract_reduce 2017-09-15 13:59:18 -07:00
Andrew Zonenberg 3404934c9c extract_reduce now only removes the head of the chain, relying on "clean" to delete upstream cells. Added "-allow-off-chain" flag, but it's currently ignored. 2017-09-15 13:59:05 -07:00
Clifford Wolf ce78717e36 Merge pull request #412 from azonenberg/reduce-fixes 
extract_reduce: Fix segfault on "undriven" inputs
 2017-09-14 22:36:25 +02:00
Robert Ou ab1bf8d661 extract_reduce: Fix segfault on "undriven" inputs 
This is easily triggered when un-techmapping if the technology-specific
cell library isn't loaded. Outputs of technology-specific cells will be
seen as inputs, and nets using those outputs will be seen as undriven.
Just ignore these cells because they can't be part of a reduce chain
anyways.
 2017-09-14 12:54:44 -07:00
Andrew Zonenberg 367d6b2194 Fixed bug where counter extraction on non-GreenPAK devices incorrectly handled parallel counter output 2017-09-14 10:27:10 -07:00
Andrew Zonenberg c8f2f082c6 Added support for inferring counters with reset to full scale instead of zero 2017-09-14 10:26:43 -07:00
Andrew Zonenberg 122532b7e1 Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted. 2017-09-14 10:26:32 -07:00
Andrew Zonenberg 0484ad666d Added support for inferring counters with active-low reset 2017-09-14 10:26:21 -07:00
Andrew Zonenberg a84172b23b Initial support for extraction of counters with clock enable 2017-09-14 10:26:10 -07:00
Andrew Zonenberg c4a70a8cc3 Fixed typo in comment. Fixed bug where extract_counter would create up counters when it meant to create down counters. 2017-09-14 10:25:51 -07:00
Clifford Wolf 7d41c5e177 Further improve extract_fa (but still buggy) 2017-09-02 16:39:17 +02:00
Clifford Wolf 18609f3df8 Merge branch 'master' of github.com:cliffordwolf/yosys 2017-09-01 12:35:09 +02:00
Clifford Wolf 8a66bd30c6 Update more stuff to use get_src_attribute() and set_src_attribute() 2017-09-01 12:26:55 +02:00
Jason Lowdermilk 8dc6083de7 updated to use get_src_attribute() and set_src_attribute(). 2017-08-31 14:51:56 -06:00
Andrew Zonenberg ed1e3ed39b extract_counter: Added optimizations to remove unused high-order bits 2017-08-30 18:15:12 -07:00
Andrew Zonenberg 634f18be96 extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos 2017-08-30 16:28:25 -07:00
Jason Lowdermilk 32c0f1193e Add support for source line tracking through synthesis phase 2017-08-29 14:46:35 -06:00
Andrew Zonenberg 3fc1b9f3fd Finished refactoring counter extraction to be nice and generic. Implemented techmapping from $__COUNT_ to GP_COUNTx cells. 2017-08-28 22:18:57 -07:00
Andrew Zonenberg 46b01f05bb Refactored extract_counter to be generic vs GreenPAK specific 2017-08-28 22:18:47 -07:00
Andrew Zonenberg b5c15636c5 Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to techmap/ since it's going to become a generic pass 2017-08-28 22:18:34 -07:00
Clifford Wolf 908f34aafc Rename recover_reduce to extract_reduce, fix args handling 2017-08-28 19:52:06 +02:00
Clifford Wolf 3aad3ed3da Merge branch 'recover-reduce' of https://github.com/azonenberg/yosys into azonenberg-recover-reduce 2017-08-28 19:46:17 +02:00
Clifford Wolf ebbb0e9479 Further improve extract_fa pass 2017-08-28 19:43:26 +02:00
Robert Ou 849b885775 recover_reduce: Update documentation 
The documentation now describes the commands performed in the deleted
recover_reduce script.
 2017-08-27 02:19:19 -07:00
Robert Ou 74d0f17fd4 recover_reduce: Reindent using tabs 2017-08-27 02:12:41 -07:00
Robert Ou 8a5887464c recover_reduce: Rename recover_reduce_core to recover_reduce 
Clifford has commented on PR #387 stating that he does not like the
driver script and would prefer to only have the core script with
appropriate notes in the documentation.

Also rename to .cc (rather than .cpp) for consistency.
 2017-08-27 02:01:32 -07:00
Robert Ou 99dad40ed0 recover_reduce: Add driver script for the $reduce_* recover feature 
Conflicts:
	passes/techmap/Makefile.inc
 2017-08-27 01:57:20 -07:00
Robert Ou 8b7dc792ee recover_reduce_core: Finish implementing the core function 2017-08-27 01:56:49 -07:00
Robert Ou fa310c98f8 recover_reduce_core: Initial commit 
Conflicts:
	passes/techmap/Makefile.inc
 2017-08-27 01:56:49 -07:00
Clifford Wolf 382cc90c65 Further improve extract_fa (seems to be fully functional now) 2017-08-25 13:41:54 +02:00
Clifford Wolf 0bf612506c Rename "adders" to "extract_fa" 2017-08-25 12:04:40 +02:00
Clifford Wolf 15cdda7c4b Towards more generic "adder" function extractor 2017-08-23 14:20:10 +02:00
Clifford Wolf 51cbec7f75 Add experimental adders pass 2017-08-22 13:52:13 +02:00
Robert Ou 9a64ba3338 abc: Allow +/ filenames in the abc command 2017-08-14 12:11:11 -07:00
Clifford Wolf 5c09f24e48 Fix typo in "abc" pass help message 2017-07-29 16:21:58 +02:00
Clifford Wolf b3bc7068d1 Fix handling of empty cell port assignments (i.e. ignore them) 2017-07-21 19:32:31 +02:00
Clifford Wolf 155a80dfb7 Fix handling of init values in "abc -dff" and "abc -clk" 2017-06-20 15:32:23 +02:00
Clifford Wolf f6421c83a2 Switched abc "clock domain not found" error to log_cmd_error() 2017-06-20 04:22:34 +02:00
Clifford Wolf fad52abf70 Add aliases for common sets of gate types to "abc -g" 2017-05-24 11:39:05 +02:00
Clifford Wolf 05cdd58c8d Add $_ANDNOT_ and $_ORNOT_ gates 2017-05-17 09:08:29 +02:00
Larry Doolittle 2021ddecb3 Squelch trailing whitespace 2017-04-12 15:11:09 +02:00
Clifford Wolf cf25dc9ce7 Copy attributes to _TECHMAP_REPLACE_ cells 2017-02-16 12:28:42 +01:00
Clifford Wolf db7314bc02 Fix techmap for inout ports connected to inout ports 2017-02-13 16:55:25 +01:00
Clifford Wolf 8927e19b13 Update ABC scripts to use "&nf" instead of "map" 2017-02-01 11:15:20 +01:00
Clifford Wolf 55785a96eb Improved ABC default scripts 2016-11-19 18:20:54 +01:00
Clifford Wolf 74702b04c2 Build fixes for VS 2015 2016-10-16 20:37:02 +02:00
Clifford Wolf e4c5ee9b89 Avoid using strcasecmp() 2016-10-14 18:20:36 +02:00
Clifford Wolf ffbb4e992e Added MEMID handling to "flatten" pass 2016-10-14 10:36:37 +02:00
Clifford Wolf ee91350add Added "zinit" pass 2016-10-12 12:05:19 +02:00
Clifford Wolf 8ebba8a35f Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00
Clifford Wolf d8ad889594 Bugfix in techmap parameter handling 2016-09-14 20:46:54 +02:00