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5293 Commits

Author SHA1 Message Date
Miodrag Milanovic ece551eaff Add files to ignore for python build 2019-05-26 09:31:43 +02:00
Eddie Hung d4fb6cac7c Revert enable check 2019-05-25 12:55:57 -07:00
Clifford Wolf a90eec12c9
Merge pull request #1041 from YosysHQ/clifford/fix1040 
Fix handling of offset and upto module ports in write_blif
 2019-05-25 19:17:05 +02:00
Clifford Wolf 6352df42ae Fix handling of offset and upto module ports in write_blif, fixes #1040 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-25 17:45:14 +02:00
Eddie Hung f3e86e06e6 Fix init 2019-05-24 18:43:26 -07:00
Eddie Hung e1cb1bb948 Fix typos 2019-05-24 18:34:27 -07:00
Eddie Hung d15da4bc11 Add more tests 2019-05-24 18:33:18 -07:00
Eddie Hung 4bd9465ed3 Call proc 2019-05-24 18:32:02 -07:00
Eddie Hung 822d0b7789 opt_rmdff to optimise even in presence of enable signal, even removing 2019-05-24 18:30:51 -07:00
Eddie Hung f0c6b73b72 Fix duplicate driver 2019-05-24 17:44:57 -07:00
Eddie Hung 0d66103cbb Add comments 2019-05-24 16:33:10 -07:00
Eddie Hung 357b1de6bc Resolve @cliffordwolf review, set even if !has_init 2019-05-24 16:15:22 -07:00
Clifford Wolf b7dd7c2dcd Add proper error message for btor recursion_guard 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-24 16:22:34 +02:00
Eddie Hung 67a4850e35
Merge pull request #1036 from YosysHQ/eddie/xilinx_dram 
Add "min bits" and "min wports" to xilinx dram rules
 2019-05-23 13:13:10 -07:00
Eddie Hung 5ac7e38d0a Fix spacing 2019-05-23 12:58:30 -07:00
Eddie Hung 99a3fee8f4 Add "min bits" and "min wports" to xilinx dram rules 2019-05-23 11:32:28 -07:00
Eddie Hung 47f9ea142f Add opt_rmdff tests 2019-05-23 11:26:38 -07:00
Eddie Hung 50ed34a6d0 opt_rmdff to work on $dffe and $_DFFE_* 2019-05-23 11:26:18 -07:00
Stefan Biereigel 85de9d26c1 fix assignment of non-wires 2019-05-23 17:55:56 +02:00
Stefan Biereigel c2caf85f7c add simple test case for wand/wor 2019-05-23 13:57:27 +02:00
Stefan Biereigel fd003e0e97 fix indentation across files 2019-05-23 13:57:27 +02:00
Stefan Biereigel 075a48d3fa implementation for assignments working 2019-05-23 13:57:27 +02:00
Stefan Biereigel 9df04d7e75 make lexer/parser aware of wand/wor net types 2019-05-23 13:57:27 +02:00
Clifford Wolf ca46947354
Merge pull request #1031 from mdaiter/optimizeLookupTableBtor 
Optimize numberOfPermutations
 2019-05-23 13:52:48 +02:00
Matthew Daiter f0ff31ceea Optimize numberOfPermutations 2019-05-22 17:29:50 -04:00
Kaj Tuomi 29b898cf76 OS X related fixes. 2019-05-22 22:58:12 +03:00
Clifford Wolf e3f9ccf56d Keep zero-width wires in opt_clean if and only if they are ports, fixes #1023 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-22 13:57:36 +02:00
Clifford Wolf 0971f772d7 Fix handling of warning and error messages within log_make_debug-blocks 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-22 13:46:38 +02:00
Clifford Wolf 5c164d0863
Merge pull request #1019 from YosysHQ/clifford/fix1016 
Add "wreduce -keepdc"
 2019-05-22 13:29:04 +02:00
Clifford Wolf 84d91420e4
Merge pull request #1021 from ucb-bar/fixfirrtl_shr,neg 
Fix static shift operands, neg result type, minor formatting
 2019-05-22 12:01:19 +02:00
Eddie Hung cb24d23b6d
Merge pull request #1024 from YosysHQ/eddie/fix_Wmissing_braces 2019-05-21 18:20:58 -07:00
Eddie Hung 7057753427 Rename label 2019-05-21 18:20:31 -07:00
Eddie Hung b5a29460b9 Try again 2019-05-21 17:20:19 -07:00
Eddie Hung 1bff09f2ff Fix warning 2019-05-21 16:26:20 -07:00
Jim Lawson a5131e2896 Fix static shift operands, neg result type, minor formatting 
Static shift operands must be constants.
The result of FIRRTL's neg operator is signed.
Fix poor indentation for gen_read().
 2019-05-21 13:04:56 -07:00
Jim Lawson 489c555b41 Merge remote-tracking branch 'upstream/master' 2019-05-21 12:47:55 -07:00
Clifford Wolf c4b8575f43 Add "wreduce -keepdc", fixes #1016 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-20 15:36:13 +02:00
Clifford Wolf c907899422
Merge pull request #1017 from Kmanfi/bigger_verilog_files 
Read bigger Verilog files.
 2019-05-18 16:54:47 +02:00
Kaj Tuomi 48ddbe52fb Read bigger Verilog files. 
Hit parser limit with 3M gate design. This commit fix it.
 2019-05-18 14:20:30 +03:00
Clifford Wolf b6345b111d
Merge pull request #1013 from antmicro/parameter_attributes 
Support for attributes on parameters and localparams for Verilog frontend
 2019-05-16 14:21:18 +02:00
Maciej Kurc 1f52332b8d Added tests for Verilog frontent for attributes on parameters and localparams 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-05-16 12:53:43 +02:00
Maciej Kurc ce4a0954bc Added support for parsing attributes on parameters in Verilog frontent. Content of those attributes is ignored. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-05-16 12:44:16 +02:00
Clifford Wolf c9def5407c
Merge pull request #1012 from YosysHQ/clifford/sigspecrw 
Another rounds of opt_clean improvements
 2019-05-15 21:00:56 +02:00
Clifford Wolf a21a84b3b4 Improvements in opt_clean 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-15 16:01:28 +02:00
Clifford Wolf 287de4b848 Add rewrite_sigspecs2, Improve remove() wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-15 16:01:00 +02:00
Clifford Wolf f67ec1b235 Do not leak file descriptors in cover.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-15 13:51:02 +02:00
Clifford Wolf 4fd0e11214
Merge pull request #1011 from hzeller/fix-constructing-string-from-int 
Fix two instances of integer-assignment to string.
 2019-05-15 13:35:52 +02:00
Clifford Wolf 64b604207d
Merge pull request #1010 from hzeller/yacc-self-contained 
Make the generated *.tab.hh include all the headers needed
 2019-05-15 13:29:55 +02:00
Clifford Wolf 36841f3911
Merge pull request #1008 from thasti/fix_libyosys_build 
Create $(LIBDIR) to fix broken build in isolated environments
 2019-05-15 13:28:52 +02:00
David Shah 3ef88ffbb2
Merge pull request #1005 from smunaut/ice40_hfosc_trim 
ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC
 2019-05-15 08:20:50 +01:00