Commit Graph

12973 Commits

Author SHA1 Message Date
Catherine c4c55cb565
Merge pull request #4134 from whitequark/cxxrtl-capture-print
CXXRTL: Allow capturing `$print` cell output
2024-01-17 13:13:15 +00:00
github-actions[bot] 37a6c9a097 Bump version 2024-01-17 00:16:14 +00:00
Catherine 5a1fcdea13 cxxrtl: include attributes in `performer::on_print` callback.
This is useful primarily to determine the source location, but can also
be used for any other purpose.
2024-01-16 16:39:11 +00:00
Catherine 905f07c03f cxxrtl: introduce `performer`, a context object for `eval()`. (breaking change)
At the moment the only thing it allows is redirecting `$print` cell
output in a context-dependent manner. In the future, it will allow
customizing handling of `$check` cells (where the default is to abort),
of out-of-range memory accesses, and other runtime conditions with
effects.

This context object also allows a suitably written testbench to add
Verilog-compliant `$time`/`$realtime` handling, albeit it involves
the ceremony of defining a `performer` subclass. Most people will
want something like this to customize `$time`:

    int64_t time = 0;
    struct : public performer {
      int64_t *time_ptr;
      int64_t time() const override { return *time_ptr; }
    } performer = { &time };

    p_top.step(&performer);
2024-01-16 16:37:07 +00:00
Catherine 02e3d508fa cxxrtl: remove `module::steps`. (breaking change)
This approach to tracking simulation time was a mistake that I did not
catch in review. It has several issues:
1. There is absolutely no requirement to call `step()`, as it is
   a convenience function. In particular, `steps` will not be
   incremented in submodules if `-noflatten` is used.
2. The semantics of `steps` does not match that of the Verilog `$time`
   construct.
3. There is no way to make the semantics of `%t` match that of Verilog.
4. The `module` interface is intentionally very barebones. It is little
   more than a container for three method pointers, `reset`, `eval`,
   and `commit`. Adding ancillary data to it goes against this.

If similar functionality is introduced again it should probably be
a variable that is global per toplevel design using some object that is
unique for an entire hierarchy of modules, and ideally exposed via
the C API. For now, it is being removed (in this commit) and (in next
commit) the capability is being reintroduced through a context object
that can be specified for `eval()`.
2024-01-16 16:35:51 +00:00
Catherine a33acb7cd9 cxxrtl: refactor the formatter and use a closure.
This commit achieves three roughly equally important goals:
1. To bring the rendering code in kernel/fmt.cc and in cxxrtl.h as close
   together as possible, with an ideal of only having the bigint library
   as the difference between the render functions.
2. To make the treatment of `$time` and `$realtime` in CXXRTL closer to
   the Verilog semantics, at least in the formatting code.
3. To change the code generator so that all of the `$print`-to-`string`
   conversion code is contained inside of a closure.

There are two reasons to aim for goal (3):
a. Because output redirection through definition of a global ostream
   object is neither convenient nor useful for environments where
   the output is consumed by other code rather than being printed on
   a terminal.
b. Because it may be desirable to, in some cases, ignore the `$print`
   cells that are present in the netlist based on a runtime decision.
   This is doubly true for an upcoming `$check` cell implementing
   assertions, since failing a `$check` would by default cause a crash.
2024-01-16 16:35:51 +00:00
Catherine bf1a99da09 cxxrtl: make observer methods non-virtual. (breaking change)
This avoids having to devirtualize them later to get performance back,
and simplifies the code a bit.

The change is prompted by the desire to add a similar observer object
to `eval()`, and a repeated consideration of whether the dispatch on
these should be virtual in first place.
2024-01-16 09:58:21 +00:00
Catherine ed81cc5f81 cxxrtl: rename observer::{on_commit→on_update}. (breaking change)
The name `on_commit` was terrible since it would not be called, as one
may conclude from the name, on each `commit()`, but only whenever that
method actually updates a value.
2024-01-16 09:58:21 +00:00
Miodrag Milanovic bd956d76ba Next dev cycle 2024-01-16 08:16:07 +01:00
Miodrag Milanovic a5c7f69ed8 Release version 0.37 2024-01-16 08:13:21 +01:00
github-actions[bot] 740265bfbd Bump version 2024-01-16 00:16:26 +00:00
N. Engelhardt fb4eeb1344 show: allow setting colors via selection on PROC boxes 2024-01-15 17:47:59 +01:00
Martin Povišer 149bcd88ad
Merge pull request #4026 from uis246/fix-format
Fix printf formats
2024-01-15 16:04:11 +01:00
Martin Povišer 568418b50b opt_lut: Replace `-dlogic` with `-tech ice40` 2024-01-15 12:35:21 +01:00
uis 5902b2826d Fix printf formats 2024-01-15 12:07:54 +01:00
github-actions[bot] fac843f480 Bump version 2024-01-15 00:17:14 +00:00
Martin Povišer 728110710e
Merge pull request #4131 from daglem/fix-initial-display
Restore sim output from initial $display
2024-01-14 17:21:44 +01:00
Dag Lem acf916f654 Restore sim output from initial $display 2024-01-14 16:52:51 +01:00
github-actions[bot] 1eb823bd0e Bump version 2024-01-12 00:16:23 +00:00
Catherine 782572895b
Merge pull request #4129 from daglem/simulation-display
Pass `$display` et al. in `initial` blocks on to `sim`
2024-01-11 16:03:29 +00:00
Catherine 7142e20dab write_cxxrtl: support initial `$print` cells. 2024-01-11 15:27:21 +01:00
Catherine d493225313 write_cxxrtl: reset state value of comb `$print` cells. 2024-01-11 15:17:06 +01:00
Catherine 1159e48721 write_verilog: emit `initial $display` correctly. 2024-01-11 13:13:04 +01:00
Catherine 0486f61a35 write_verilog: emit zero width parameters as `.PARAM()`. 2024-01-11 13:13:04 +01:00
Dag Lem 3ed9030eb4 Optionally suppress output from display system tasks in read_verilog 2024-01-11 13:12:53 +01:00
Jannis Harder 510d137996 fmt: Allow non-constant $display calls in initial blocks
These are useful for formal verification with SBY where they can be used
to display solver chosen `rand const reg` signals and signals derived
from those.

The previous error message for non-constant initial $display statements
is downgraded to a log message. Constant initial $display statements
will be shown both during elaboration and become part of the RTLIL so
that the `sim` output is complete.
2024-01-11 13:01:28 +01:00
Jannis Harder 57b4e16acd sim: Include $display output in JSON summary
This allows tools like SBY to capture the $display output independent
from anything else sim might log. Additionally it provides source and
hierarchy locations for everything printed.
2024-01-11 12:01:39 +01:00
Martin Povišer eeadbb583e
Merge pull request #4069 from daglem/simplify-array-slice-assignment
Simplify and correct array slice assignment
2024-01-11 11:41:34 +01:00
hakan-demirli 1a4bea82a1
Merge branch 'YosysHQ:master' into master 2024-01-11 09:33:53 +03:00
github-actions[bot] f26495e54d Bump version 2024-01-11 00:16:28 +00:00
Dag Lem e0566eafdb Add test for rhs sign extension in array slice assignment 2024-01-10 21:15:00 +01:00
Dag Lem 23cd23efc5 Simplify and correct AST for array slice assignment
Corrects sign extension of the right hand side, and hopefully
makes the code simpler to understand.

Fixes #4064
2024-01-10 21:15:00 +01:00
Martin Povišer a921f5968e
Merge pull request #3875 from daglem/nowrshmsk-optimization
Optimization of nowrshmsk
2024-01-10 21:08:17 +01:00
Dag Lem 1a2b4759e8 Assign from rvalue via temporary register in nowrshmsk CASE
Avoid repeating complex rvalue expressions for each condition.
2024-01-10 20:40:01 +01:00
Dag Lem dbec704b49 Include x bits in test of lhs dynamic part-select 2024-01-10 20:28:36 +01:00
Dag Lem a105d2c050 Add torture test for (* nowrshmsk *) stride optimization 2024-01-10 20:28:36 +01:00
Dag Lem 2cab4ff173 Correction and optimization of nowrshmsk
This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that
nowrshmsk is actually tested.

Stride is extracted from indexing of two-dimensional packed arrays and
variable slices on the form dst[i*stride +: width] = src, and is used
to optimize the generated CASE block.

Also uses less confusing variable names for indexing of lhs wires.
2024-01-10 20:28:36 +01:00
github-actions[bot] e131a7895a Bump version 2024-01-10 00:16:19 +00:00
Catherine bc9206f0f5 write_verilog: emit `casez` as `if/elif/else` whenever possible. 2024-01-09 14:49:20 +00:00
Miodrag Milanović 9e3d132050
Merge pull request #4121 from YosysHQ/macos_upgrade
Update macOS to Ventura
2024-01-09 15:05:15 +01:00
Catherine f6e36f0e54 cxxrtl: implement a generic record/replay interface.
This commit adds a reader/writer implementation for a file format
optimized for fast, single-pass storage and retrieval of design state
changes, as well as a recorder/replayer that integrate with the eval
and commit simulation steps to create replay logs and reproduce them
later.

This feature makes it possible to run a simulation once, recording
the stimulus as well as changes to the registers, and navigate to
a past time point in the simulation later without rerunning it.
Both the changes in inputs (stimulus) and changes in state are saved
so that navigation does not require calling `eval()` or `commit()`;
only a series of memory copy operations.

On a representative example of a SoC netlist, saving the replay log
while simulating it takes 150% of the time it would take to simulate
the same design without logging, which is a much lower overhead than
writing an equivalent full view (including memories) VCD waveform dump.
The replay log is also several times smaller than the VCD dump, and
more space savings are available as low hanging fruit.

Replaying the log has not been optimized and currently takes about
the same time as running the simulation in first place. However, it
is still useful since it provides fast navigation to an arbitrary time
point, something that rerunning the simulation does not allow for.

The current file format should be considered preliminary. It is not
very space-efficient, and my testing shows that a lot of time is spent
in the write() syscall in the kernel. Most likely, compression and/or
writing in another thread could improve performance by 10-20%. This
may be done at a later time.
2024-01-09 13:48:36 +00:00
Catherine a59d477098 cxxrtl: improve robustness of `cxxrtl::time`.
Avoid overflow during conversion for any representable raw value.
2024-01-09 13:44:39 +00:00
Catherine 5aaf1f1d39 cxxrtl: implement `value.get()` and `value.set()` for signed types. 2024-01-09 13:44:39 +00:00
Miodrag Milanovic c045c9a5c9 Update macOS to Ventura 2024-01-09 10:58:31 +01:00
github-actions[bot] 22370ad21e Bump version 2024-01-09 00:16:54 +00:00
N. Engelhardt 5a4db62870
Merge pull request #4111 from povik/verilog-back-nonpruned-case
write_verilog: Handle edge case with non-pruned processes
2024-01-08 16:38:56 +01:00
hakan-demirli e093f57c10 fix: fail if neither HOME nor XDG_STATE_HOME are set 2024-01-08 08:49:04 +03:00
hakan-demirli 54c3b63d24 fix: third time is the charm 2024-01-07 14:34:27 +03:00
hakan-demirli 31b45c9555 fix: xdg spec for hist 2024-01-07 14:17:48 +03:00
hakan-demirli bcf1c7b879
Merge branch 'YosysHQ:master' into master 2024-01-07 14:08:35 +03:00