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9677 Commits

Author SHA1 Message Date
Eddie Hung 53fc3ed645 aiger: -xaiger to read $_DFF_[NP]_ back with new clocks created 
according to mergeability class, and init state as cell attr
 2020-05-14 10:33:56 -07:00
Eddie Hung ffa52738fb xaiger: output $_DFF_[NP]_ with mergeability if -dff option 2020-05-14 10:33:56 -07:00
Eddie Hung 65395168a0 logger: fix for multiple calls with same pattern 2020-05-14 10:32:07 -07:00
Alberto Gonzalez 299ab76a09
smtbmc: Fix return status handling. 2020-05-14 17:07:59 +00:00
Eddie Hung cd92a706ae Fix whitespace 2020-05-14 09:51:17 -07:00
Eddie Hung 5bcde7ccc3
Merge pull request #2045 from YosysHQ/eddie/fix2042 
verilog: error if no direction given for task arguments, default to input in SV mode
 2020-05-14 09:45:54 -07:00
Claire Wolf f02e20907e
Merge pull request #2052 from YosysHQ/claire/verific_memfix 
Add support for non-power-of-two mem chunks in verific importer
 2020-05-14 18:45:13 +02:00
Claire Wolf 140e9a8e06
Merge pull request #2050 from YosysHQ/eddie/opt_clean_fixes 
opt_clean: remove (* init *) regardless of -purge, remove (* init *) when consistent with sigmap, clean to behave identically
 2020-05-14 18:31:16 +02:00
Claire Wolf ee0beb481d
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto 
ast: swap range regardless of range_left >= 0
 2020-05-14 18:06:18 +02:00
Eddie Hung 56a5b1d2da test: add another testcase as per @nakengelhardt 2020-05-14 08:36:36 -07:00
Claire Wolf 173aa27ca5 Add support for non-power-of-two mem chunks in verific importer 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-14 14:38:13 +02:00
Xiretza 204e8b6fc6
Suppress warning during initial clone of ABC repo 
9dedac50 introduced this harmless but disconcerting warning, which was emitted
when abc/ did not yet exist and was about to be cloned:

/bin/sh: line 0: cd: abc: No such file or directory
 2020-05-14 11:18:35 +02:00
Eddie Hung 5be4b00a0d opt_clean: improve warning message 2020-05-14 00:59:38 -07:00
Eddie Hung aa4a69f89b opt_clean: add init test 2020-05-14 00:31:08 -07:00
Eddie Hung fc9fb09a91 opt_clean: rminit without -purge; also remove if consistent with const.. 
warn otherwise
 2020-05-14 00:31:08 -07:00
Eddie Hung 68b31f5e99 opt_clean: really make 'clean' identical to 'opt_clean' by rminit too 2020-05-14 00:31:08 -07:00
Eddie Hung 237962debd verilog: default to input in sv mode if task/func has no dir ... 
otherwise error
 2020-05-13 13:33:37 -07:00
Eddie Hung 0d2c33f9f4 tests: update/extend task argument tests 2020-05-13 10:11:45 -07:00
Peter Crozier 495dcfc812 Consolidate Linux and Mac version of YS_DEBUGTRAP_IF_DEBUGGING. 2020-05-13 14:17:00 +01:00
Peter Crozier 3988f935b8 Extend YS_DEBUGTRAP to MacOS. 2020-05-13 13:11:49 +01:00
Eddie Hung 27b7ffc754 ice40: fix ICESTORM_LC process sensitivity 2020-05-12 15:40:48 -07:00
Eddie Hung 4ecae8a673 ice40: fix whitespace 2020-05-12 15:40:13 -07:00
David Shah 95fb3cf487 ecp5: Add missing SERDES parameters 
Signed-off-by: David Shah <dave@ds0.me>
 2020-05-12 21:12:26 +01:00
Eddie Hung 1f3003be7d verilog: error out when non-ANSI task/func arguments 2020-05-11 13:00:36 -07:00
Eddie Hung e5ce5a4fd5 tests: add #2042 testcase 2020-05-11 11:05:19 -07:00
Eddie Hung b11cf67a81 Setup tests/verilog properly 2020-05-11 10:31:02 -07:00
Eddie Hung 49e64ad492 test: update opt_expr_alu test 2020-05-08 11:12:58 -07:00
Eddie Hung 9694dc42dd opt_expr: consume_x to require/imply !keepdc 2020-05-08 11:12:43 -07:00
Eddie Hung 17f4e06247 opt_expr: restore consume_x; use for coarse grained too 2020-05-08 11:07:44 -07:00
Eddie Hung 495acf9815 tests: opt_expr tests that depend on consumex 2020-05-08 11:07:11 -07:00
Claire Wolf aafaeb66df
Merge pull request #2038 from nakengelhardt/no-libdir-flag 
Remove yosys libdir from LDFLAGS (and fix a typo)
 2020-05-08 10:40:25 +02:00
Claire Wolf 8ec3b6db1c Fix clang compiler warning 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-08 10:13:39 +02:00
whitequark ebfdf61eb9
Merge pull request #2022 from Xiretza/fallthroughs 
Avoid switch fall-through warnings
 2020-05-08 05:30:32 +00:00
Dan Ravensloft 5b779f7f4e intel_alm: direct LUTRAM cell instantiation 
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.

While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
 2020-05-07 21:03:13 +02:00
N. Engelhardt c9befa769f Remove yosys libdir from LDFLAGS (and fix a typo) 2020-05-07 19:28:18 +02:00
Claire Wolf 0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990 
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
 2020-05-07 18:11:48 +02:00
Eddie Hung 3a985d8285
Merge pull request #2034 from YosysHQ/eddie/abc_remote 
Makefile: git fetch $(ABCURL) explicitly for local ABC checkout
 2020-05-07 08:07:42 -07:00
Xiretza d86fc791f9
Reorder cases to avoid fall-through warning 
log_assert(false) never returns and thus can't fall through, but gcc
doesn't seem to think that far. Making it the last case avoids the
problem entirely.
 2020-05-07 13:39:34 +02:00
Xiretza 695150b037
Add YS_FALLTHROUGH macro to mark case fall-through 
C++17 introduced [[fallthrough]], GCC and clang had their own vendored
attributes before that. MSVC doesn't seem to have such a warning at all.
 2020-05-07 13:39:34 +02:00
Eddie Hung 8eb98b12c7 Makefile: git fetch all commits from $(ABCURL) repo 2020-05-06 16:23:46 -07:00
Sahand Kashani 1688a62500 Formatting fixes 2020-05-06 21:15:32 +02:00
Eddie Hung a299e606f8
Merge pull request #2028 from zachjs/master 
verilog: allow null gen-if then block
 2020-05-06 12:10:28 -07:00
Zachary Snow 8f9bba1bbf verilog: allow null gen-if then block 2020-05-06 08:43:02 -04:00
Alberto Gonzalez 323aa1df75
verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace. 2020-05-06 07:22:17 +00:00
Sahand Kashani 1f1b64b880 Add extmodule support to firrtl backend 
The current firrtl backend emits blackboxes as standard modules
with an empty body, but this causes the firrtl compiler to
optimize out entire circuits due to the absence of any drivers.

Yosys already tags blackboxes with a (*blackbox*) attribute, so this
commit just propagates this change to firrtl's syntax for blackboxes.
 2020-05-06 01:01:14 +02:00
Eddie Hung 004999218f techlibs/common: more robustness when *_WIDTH = 0 2020-05-05 08:01:27 -07:00
Eddie Hung 283b1130a6
Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup 
frontend: cleanup to use more ID::*, more dict<> instead of map<>
 2020-05-05 07:59:40 -07:00
whitequark ae409d4d81
Merge pull request #2012 from whitequark/fix-wasi-abc-build 
Fix WASI builds with abc enabled
 2020-05-05 14:03:40 +00:00
Eddie Hung 5fa06e4894
Merge pull request #2026 from YosysHQ/eddie/scratchpad_abc9_W 
synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad
 2020-05-05 06:49:36 -07:00
Eddie Hung 7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src 
verilog: set src attribute for primitives
 2020-05-05 06:49:18 -07:00