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yosys
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383 Commits

Author SHA1 Message Date
Clifford Wolf 04727c7e0f No implicit conversion from IdString to anything else 2014-08-02 18:58:40 +02:00
Clifford Wolf 768eb846c4 More bugfixes related to new RTLIL::IdString 2014-08-02 18:14:21 +02:00
Clifford Wolf 08392aad8f Limit size of log_signal buffer to 100 elements 2014-08-02 15:52:21 +02:00
Clifford Wolf e590ffc84d Improvements in new RTLIL::IdString implementation 2014-08-02 15:44:10 +02:00
Clifford Wolf 60f3dc9923 Implemented new reference counting RTLIL::IdString 2014-08-02 15:11:35 +02:00
Clifford Wolf 97ad0623df Fixed memory corruption related to id2cstr() 2014-08-02 13:34:07 +02:00
Clifford Wolf b9bd22b8c8 More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
Clifford Wolf 14412e6c95 Preparations for RTLIL::IdString redesign: cleanup of existing code 2014-08-02 00:45:25 +02:00
Clifford Wolf 75ffd1643c Added logfile hash to statistics footer 2014-08-01 19:43:28 +02:00
Clifford Wolf 1e224506be Added per-pass cpu usage statistics 2014-08-01 18:42:10 +02:00
Clifford Wolf d13eb7e099 Added ModIndex helper class, some changes to RTLIL::Monitor 2014-08-01 17:14:32 +02:00
Clifford Wolf 97a17d39e2 Packed SigBit::data and SigBit::offset in a union 2014-08-01 15:25:42 +02:00
Clifford Wolf 32a1cc3efd Renamed modwalker.h to modtools.h 2014-07-31 23:30:18 +02:00
Clifford Wolf cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
Clifford Wolf b5a9e51b96 Added "trace" command 2014-07-31 15:02:16 +02:00
Clifford Wolf cd9407404a Added RTLIL::Monitor 2014-07-31 14:45:14 +02:00
Clifford Wolf e6d33513a5 Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
Clifford Wolf 1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf 6166c76831 Added "yosys -A" 2014-07-31 01:05:27 +02:00
Clifford Wolf e5c245df9d Added "yosys -Q" 2014-07-31 00:53:21 +02:00
Clifford Wolf 2541489105 Added techmap CONSTMAP feature 2014-07-30 22:04:30 +02:00
Clifford Wolf 6400ae3648 Added write_file command 2014-07-30 19:59:29 +02:00
Clifford Wolf 3f0a5746ef Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models 2014-07-30 18:37:17 +02:00
Clifford Wolf 45fd26b76e Added "log_dump_val_worker(char *v)" 2014-07-30 15:58:21 +02:00
Clifford Wolf a7c6b37abf Added "kernel/yosys.h" and "kernel/yosys.cc" 2014-07-30 14:10:15 +02:00
Clifford Wolf 273383692a Added "test_cell" command 2014-07-29 22:07:41 +02:00
Clifford Wolf e6df25bf74 Renamed "write_autotest" to "test_autotb" and moved to passes/tests/ 2014-07-29 21:12:50 +02:00
Clifford Wolf 03c96f9ce7 Added "techmap -map %{design-name}" 2014-07-29 16:35:13 +02:00
Clifford Wolf 397b00252d Added $shift and $shiftx cell types (needed for correct part select behavior) 2014-07-29 16:35:13 +02:00
Clifford Wolf 3c45277ee0 Added wire->upto flag for signals such as "wire [0:7] x;" 2014-07-28 12:12:13 +02:00
Clifford Wolf 7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf d86a25f145 Added std::initializer_list<> constructor to SigSpec 2014-07-28 10:52:58 +02:00
Clifford Wolf f99495a895 Added cover() to all SigSpec constructors 2014-07-28 10:52:30 +02:00
Clifford Wolf c4bdba78cb Added proper Design->addModule interface 2014-07-27 21:12:09 +02:00
Clifford Wolf 5da343b7de Added topological sorting to techmap 2014-07-27 16:43:39 +02:00
Clifford Wolf 0c86d6106c Added SigPool::check(bit) 2014-07-27 15:38:02 +02:00
Clifford Wolf ddd31a0b66 Small improvements in PerformanceTimer API 2014-07-27 15:14:02 +02:00
Clifford Wolf d07a871d35 Improved performance of opt_const on large modules 2014-07-27 14:50:25 +02:00
Clifford Wolf 4be645860b Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs 2014-07-27 14:47:48 +02:00
Clifford Wolf cbc3a46a97 Added RTLIL::SigSpecConstIterator 2014-07-27 14:47:23 +02:00
Clifford Wolf d878fcbdc7 Added log_cmd_error_expection 2014-07-27 12:05:50 +02:00
Clifford Wolf 675cb93da9 Added RTLIL::Module::wire(id) and cell(id) lookup functions 2014-07-27 11:18:31 +02:00
Clifford Wolf 0bd8fafbd2 Added RTLIL::Design::modules() 2014-07-27 11:18:30 +02:00
Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf d088854b47 Added conversion from ObjRange to std::vector and std::set 2014-07-27 11:18:30 +02:00
Clifford Wolf 1c8fdaeef8 Added RTLIL::ObjIterator and RTLIL::ObjRange 2014-07-27 11:18:30 +02:00
Clifford Wolf ddc5b41848 Using std::move() in SigSpec move constructor 2014-07-27 09:20:59 +02:00
Clifford Wolf 7f3dc86ecd Added RTLIL::SigSpec move constructor and move assignment operator 2014-07-27 02:11:57 +02:00
Clifford Wolf c91570bde3 Mostly cosmetic changes to rtlil.h 2014-07-27 02:00:04 +02:00
Clifford Wolf 4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf d68c993ed2 Changed more code to the new RTLIL::Wire constructors 2014-07-26 21:30:38 +02:00
Clifford Wolf 946ddff9ce Changed a lot of code to the new RTLIL::Wire constructors 2014-07-26 20:12:50 +02:00
Clifford Wolf 267c615640 Added support for here documents 2014-07-26 17:21:40 +02:00
Clifford Wolf 97a59851a6 Added RTLIL::Cell::has(portname) 2014-07-26 16:11:28 +02:00
Clifford Wolf f8fdc47d33 Manual fixes for new cell connections API 2014-07-26 15:58:23 +02:00
Clifford Wolf b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf cd6574ecf6 Added some missing "const" in rtlil.h 2014-07-26 15:58:22 +02:00
Clifford Wolf 7ac9dc7f6e Added RTLIL::Module::connections() 2014-07-26 15:58:21 +02:00
Clifford Wolf b03aec6e32 Added RTLIL::Module::connect(const RTLIL::SigSig&) 2014-07-26 14:31:47 +02:00
Clifford Wolf 3719281ed4 Automatically pack SigSpec on copy/assign 2014-07-26 13:59:30 +02:00
Clifford Wolf e75e495c2b Added new RTLIL::Cell port access methods 2014-07-26 12:22:58 +02:00
Clifford Wolf cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf 4755e14e7b Added copy-constructor-like module->addCell(name, other) method 2014-07-26 00:38:44 +02:00
Clifford Wolf 2bec47a404 Use only module->addCell() and module->remove() to create and delete cells 2014-07-25 17:56:19 +02:00
Clifford Wolf c762050e7f Added RTLIL::SigSpec is_chunk()/as_chunk() API 2014-07-25 14:23:10 +02:00
Clifford Wolf c4e4f79a2a Disabled cover() for non-linux builds 2014-07-25 12:27:36 +02:00
Clifford Wolf 7f1789ad1b Fixed typo in cover id 2014-07-25 03:41:53 +02:00
Clifford Wolf 6aa792c864 Replaced more old SigChunk programming patterns 2014-07-24 23:10:58 +02:00
Clifford Wolf 10d2402e2f Added cover_list() API 2014-07-24 20:47:18 +02:00
Clifford Wolf 2f54345cff Added "cover" command 2014-07-24 16:14:19 +02:00
Clifford Wolf e589289df7 Some improvements in SigSpec packing/unpacking and checking 2014-07-24 15:05:41 +02:00
Clifford Wolf 7679000673 Now using a dedicated ELF section for all coverage counters 2014-07-24 15:05:05 +02:00
Clifford Wolf 22ede43b3f Small changes regarding cover() and check() in SigSpec 2014-07-24 04:46:36 +02:00
Clifford Wolf 798f713629 Added support for YOSYS_COVER_FILE env variable 2014-07-24 04:16:32 +02:00
Clifford Wolf 1b0d5fc22d Added cover() calls to RTLIL::SigSpec methods 2014-07-24 03:50:28 +02:00
Clifford Wolf 9cf12570ba Added support for YOSYS_COVER_DIR env variable 2014-07-24 03:49:32 +02:00
Clifford Wolf 6b1018314c Added cover() API 2014-07-24 03:48:38 +02:00
Clifford Wolf 82fa356037 Added hashing to RTLIL::SigSpec relational and equal operators 2014-07-23 23:58:03 +02:00
Clifford Wolf f368d792fb Disabled RTLIL::SigSpec::check() in release builds 2014-07-23 21:42:44 +02:00
Clifford Wolf 95ac484548 Fixed release build 2014-07-23 21:38:18 +02:00
Clifford Wolf 2a41afb7b2 Added RTLIL::SigSpec::repeat() 2014-07-23 21:34:14 +02:00
Clifford Wolf c094c53de8 Removed RTLIL::SigSpec::optimize() 2014-07-23 20:32:28 +02:00
Clifford Wolf 8fd8e4a468 Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always optimized 2014-07-23 20:11:55 +02:00
Clifford Wolf a62c21c9c6 Removed RTLIL::SigSpec::expand() method 2014-07-23 19:34:51 +02:00
Clifford Wolf 4e802eb7f6 Fixed all users of SigSpec::chunks_rw() and removed it 2014-07-23 15:36:09 +02:00
Clifford Wolf 85db102e13 Replaced RTLIL::SigSpec::operator!=() with inline version 2014-07-23 15:35:09 +02:00
Clifford Wolf ec923652e2 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 2014-07-23 09:52:55 +02:00
Clifford Wolf a8d3a68971 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 2014-07-23 09:49:43 +02:00
Clifford Wolf 260c19ec5a Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3 2014-07-23 09:34:47 +02:00
Clifford Wolf c61467a32c Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&) 2014-07-23 08:59:54 +02:00
Clifford Wolf 115dd959d9 SigSpec refactoring: More cleanups of old SigSpec use pattern 2014-07-22 23:50:21 +02:00
Clifford Wolf 9e94f41b89 SigSpec refactoring: Added RTLIL::SigSpecIterator 2014-07-22 23:49:26 +02:00
Clifford Wolf f80da7b41d SigSpec refactoring: added RTLIL::SigSpec::operator[] 2014-07-22 22:54:03 +02:00
Clifford Wolf fd4cbe6275 SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked form 2014-07-22 22:26:30 +02:00
Clifford Wolf a97be0828a Removed RTLIL::SigChunk::compare() 2014-07-22 21:40:52 +02:00
Clifford Wolf 08e1e25169 SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api 2014-07-22 21:33:52 +02:00
Clifford Wolf 28b3fd05fa SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw() 2014-07-22 20:58:44 +02:00
Clifford Wolf 7bffde6abd SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only 2014-07-22 20:39:38 +02:00
Clifford Wolf 4b4048bc5f SigSpec refactoring: using the accessor functions everywhere 2014-07-22 20:39:37 +02:00