Clifford Wolf
|
6c8b0a5fd1
|
More dict/pool related changes
|
2014-12-27 12:02:57 +01:00 |
Clifford Wolf
|
66ab88d7b0
|
More hashtable finetuning
|
2014-12-27 03:04:50 +01:00 |
Clifford Wolf
|
ec4751e55c
|
Replaced std::unordered_set (nodict) with Yosys::pool
|
2014-12-26 21:59:41 +01:00 |
Clifford Wolf
|
9e6fb0b02c
|
Replaced std::unordered_map as implementation for Yosys::dict
|
2014-12-26 21:35:22 +01:00 |
Clifford Wolf
|
a6c96b986b
|
Added Yosys::{dict,nodict,vector} container types
|
2014-12-26 10:53:21 +01:00 |
Clifford Wolf
|
edb3c9d0c4
|
Renamed extend() to extend_xx(), changed most users to extend_u0()
|
2014-12-24 09:51:17 +01:00 |
Clifford Wolf
|
76fa527492
|
Added support for multiple clock domains to "abc" pass
|
2014-12-21 16:52:05 +01:00 |
Clifford Wolf
|
6cec188c52
|
Fixed build with gcc 4.6
|
2014-12-16 10:38:25 +01:00 |
Clifford Wolf
|
7775d2806f
|
Added IdString::destruct_guard hack
|
2014-12-11 21:46:36 +01:00 |
Clifford Wolf
|
7d6e586df8
|
Added bool constructors to SigBit and SigSpec
|
2014-12-08 15:08:02 +01:00 |
Clifford Wolf
|
bca2442c67
|
Added module->addDffe() and module->addDffeGate()
|
2014-12-08 14:59:38 +01:00 |
Clifford Wolf
|
546e8b5fe7
|
Improved TopoSort determinism
|
2014-11-07 15:21:03 +01:00 |
Clifford Wolf
|
34caeeb4f3
|
Fixed a few VS warnings
|
2014-10-17 06:02:38 +02:00 |
William Speirs
|
9cb2303799
|
Made iterators extend std::iterator and added == operator
|
2014-10-15 00:56:37 +02:00 |
Clifford Wolf
|
0b8cfbc6fd
|
Added support for "keep" on modules
|
2014-09-29 12:51:54 +02:00 |
Clifford Wolf
|
00964f2f61
|
Initialize RTLIL::Const from std::vector<bool>
|
2014-09-19 15:50:55 +02:00 |
Clifford Wolf
|
8927aa6148
|
Removed $bu0 cell type
|
2014-09-04 02:07:52 +02:00 |
Clifford Wolf
|
e07698818d
|
Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data
|
2014-09-01 11:36:02 +02:00 |
Clifford Wolf
|
be44157c0f
|
Added RTLIL::Const::size()
|
2014-08-31 18:07:48 +02:00 |
Clifford Wolf
|
0b6769af3f
|
Typo fixes in cell->*Param() API
|
2014-08-31 17:43:31 +02:00 |
Clifford Wolf
|
2a1b08aeb3
|
Added design->scratchpad
|
2014-08-30 19:37:12 +02:00 |
Clifford Wolf
|
eda603105e
|
Added is_signed argument to SigSpec.as_int() and Const.as_int()
|
2014-08-24 15:14:00 +02:00 |
Clifford Wolf
|
98442e019d
|
Added emscripten (emcc) support to build system and some build fixes
|
2014-08-22 16:20:22 +02:00 |
Clifford Wolf
|
b37d70dfd7
|
Added mod->addGate() methods for new gate types
|
2014-08-19 14:26:54 +02:00 |
Clifford Wolf
|
7f734ecc09
|
Added module->uniquify()
|
2014-08-16 23:50:36 +02:00 |
Clifford Wolf
|
f092b50148
|
Renamed $_INV_ cell type to $_NOT_
|
2014-08-15 14:11:40 +02:00 |
Clifford Wolf
|
ca87116449
|
More idstring sort_by_* helpers and fixed tpl ordering in techmap
|
2014-08-15 02:40:46 +02:00 |
Clifford Wolf
|
978a933b6a
|
Added RTLIL::SigSpec::to_sigbit_map()
|
2014-08-14 23:14:47 +02:00 |
Clifford Wolf
|
2f44d8ccf8
|
Added sig.{replace,remove,extract} variants for std::{map,set} pattern
|
2014-08-14 22:32:18 +02:00 |
Clifford Wolf
|
1bf7a18fec
|
Added module->ports
|
2014-08-14 16:22:52 +02:00 |
Clifford Wolf
|
13f2f36884
|
RIP $safe_pmux
|
2014-08-14 11:39:46 +02:00 |
Clifford Wolf
|
e5ac8fdf2b
|
Fixed SigBit(RTLIL::Wire *wire) constructor
|
2014-08-12 15:39:48 +02:00 |
Clifford Wolf
|
523df73145
|
Added support for truncating of wires to wreduce pass
|
2014-08-05 14:47:03 +02:00 |
Clifford Wolf
|
ebbbe7fc83
|
Added RTLIL::IdString::in(...)
|
2014-08-04 15:40:07 +02:00 |
Clifford Wolf
|
8e7361f128
|
Removed at() method from RTLIL::IdString
|
2014-08-02 19:08:02 +02:00 |
Clifford Wolf
|
04727c7e0f
|
No implicit conversion from IdString to anything else
|
2014-08-02 18:58:40 +02:00 |
Clifford Wolf
|
768eb846c4
|
More bugfixes related to new RTLIL::IdString
|
2014-08-02 18:14:21 +02:00 |
Clifford Wolf
|
08392aad8f
|
Limit size of log_signal buffer to 100 elements
|
2014-08-02 15:52:21 +02:00 |
Clifford Wolf
|
e590ffc84d
|
Improvements in new RTLIL::IdString implementation
|
2014-08-02 15:44:10 +02:00 |
Clifford Wolf
|
60f3dc9923
|
Implemented new reference counting RTLIL::IdString
|
2014-08-02 15:11:35 +02:00 |
Clifford Wolf
|
97ad0623df
|
Fixed memory corruption related to id2cstr()
|
2014-08-02 13:34:07 +02:00 |
Clifford Wolf
|
b9bd22b8c8
|
More cleanups related to RTLIL::IdString usage
|
2014-08-02 13:19:57 +02:00 |
Clifford Wolf
|
14412e6c95
|
Preparations for RTLIL::IdString redesign: cleanup of existing code
|
2014-08-02 00:45:25 +02:00 |
Clifford Wolf
|
d13eb7e099
|
Added ModIndex helper class, some changes to RTLIL::Monitor
|
2014-08-01 17:14:32 +02:00 |
Clifford Wolf
|
97a17d39e2
|
Packed SigBit::data and SigBit::offset in a union
|
2014-08-01 15:25:42 +02:00 |
Clifford Wolf
|
cdae8abe16
|
Renamed port access function on RTLIL::Cell, added param access functions
|
2014-07-31 16:38:54 +02:00 |
Clifford Wolf
|
cd9407404a
|
Added RTLIL::Monitor
|
2014-07-31 14:45:14 +02:00 |
Clifford Wolf
|
e6d33513a5
|
Added module->design and cell->module, wire->module pointers
|
2014-07-31 14:11:39 +02:00 |
Clifford Wolf
|
1cb25c05b3
|
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
|
2014-07-31 13:19:47 +02:00 |
Clifford Wolf
|
2541489105
|
Added techmap CONSTMAP feature
|
2014-07-30 22:04:30 +02:00 |
Clifford Wolf
|
a7c6b37abf
|
Added "kernel/yosys.h" and "kernel/yosys.cc"
|
2014-07-30 14:10:15 +02:00 |
Clifford Wolf
|
03c96f9ce7
|
Added "techmap -map %{design-name}"
|
2014-07-29 16:35:13 +02:00 |
Clifford Wolf
|
397b00252d
|
Added $shift and $shiftx cell types (needed for correct part select behavior)
|
2014-07-29 16:35:13 +02:00 |
Clifford Wolf
|
3c45277ee0
|
Added wire->upto flag for signals such as "wire [0:7] x;"
|
2014-07-28 12:12:13 +02:00 |
Clifford Wolf
|
7bd2d1064f
|
Using log_assert() instead of assert()
|
2014-07-28 11:27:48 +02:00 |
Clifford Wolf
|
d86a25f145
|
Added std::initializer_list<> constructor to SigSpec
|
2014-07-28 10:52:58 +02:00 |
Clifford Wolf
|
c4bdba78cb
|
Added proper Design->addModule interface
|
2014-07-27 21:12:09 +02:00 |
Clifford Wolf
|
cbc3a46a97
|
Added RTLIL::SigSpecConstIterator
|
2014-07-27 14:47:23 +02:00 |
Clifford Wolf
|
675cb93da9
|
Added RTLIL::Module::wire(id) and cell(id) lookup functions
|
2014-07-27 11:18:31 +02:00 |
Clifford Wolf
|
0bd8fafbd2
|
Added RTLIL::Design::modules()
|
2014-07-27 11:18:30 +02:00 |
Clifford Wolf
|
10e5791c5e
|
Refactoring: Renamed RTLIL::Design::modules to modules_
|
2014-07-27 11:18:30 +02:00 |
Clifford Wolf
|
d088854b47
|
Added conversion from ObjRange to std::vector and std::set
|
2014-07-27 11:18:30 +02:00 |
Clifford Wolf
|
1c8fdaeef8
|
Added RTLIL::ObjIterator and RTLIL::ObjRange
|
2014-07-27 11:18:30 +02:00 |
Clifford Wolf
|
ddc5b41848
|
Using std::move() in SigSpec move constructor
|
2014-07-27 09:20:59 +02:00 |
Clifford Wolf
|
7f3dc86ecd
|
Added RTLIL::SigSpec move constructor and move assignment operator
|
2014-07-27 02:11:57 +02:00 |
Clifford Wolf
|
c91570bde3
|
Mostly cosmetic changes to rtlil.h
|
2014-07-27 02:00:04 +02:00 |
Clifford Wolf
|
4c4b602156
|
Refactoring: Renamed RTLIL::Module::cells to cells_
|
2014-07-27 01:51:45 +02:00 |
Clifford Wolf
|
f9946232ad
|
Refactoring: Renamed RTLIL::Module::wires to wires_
|
2014-07-27 01:49:51 +02:00 |
Clifford Wolf
|
d68c993ed2
|
Changed more code to the new RTLIL::Wire constructors
|
2014-07-26 21:30:38 +02:00 |
Clifford Wolf
|
946ddff9ce
|
Changed a lot of code to the new RTLIL::Wire constructors
|
2014-07-26 20:12:50 +02:00 |
Clifford Wolf
|
97a59851a6
|
Added RTLIL::Cell::has(portname)
|
2014-07-26 16:11:28 +02:00 |
Clifford Wolf
|
cd6574ecf6
|
Added some missing "const" in rtlil.h
|
2014-07-26 15:58:22 +02:00 |
Clifford Wolf
|
7ac9dc7f6e
|
Added RTLIL::Module::connections()
|
2014-07-26 15:58:21 +02:00 |
Clifford Wolf
|
b03aec6e32
|
Added RTLIL::Module::connect(const RTLIL::SigSig&)
|
2014-07-26 14:31:47 +02:00 |
Clifford Wolf
|
3719281ed4
|
Automatically pack SigSpec on copy/assign
|
2014-07-26 13:59:30 +02:00 |
Clifford Wolf
|
e75e495c2b
|
Added new RTLIL::Cell port access methods
|
2014-07-26 12:22:58 +02:00 |
Clifford Wolf
|
cc4f10883b
|
Renamed RTLIL::{Module,Cell}::connections to connections_
|
2014-07-26 11:58:03 +02:00 |
Clifford Wolf
|
4755e14e7b
|
Added copy-constructor-like module->addCell(name, other) method
|
2014-07-26 00:38:44 +02:00 |
Clifford Wolf
|
2bec47a404
|
Use only module->addCell() and module->remove() to create and delete cells
|
2014-07-25 17:56:19 +02:00 |
Clifford Wolf
|
c762050e7f
|
Added RTLIL::SigSpec is_chunk()/as_chunk() API
|
2014-07-25 14:23:10 +02:00 |
Clifford Wolf
|
6aa792c864
|
Replaced more old SigChunk programming patterns
|
2014-07-24 23:10:58 +02:00 |
Clifford Wolf
|
22ede43b3f
|
Small changes regarding cover() and check() in SigSpec
|
2014-07-24 04:46:36 +02:00 |
Clifford Wolf
|
82fa356037
|
Added hashing to RTLIL::SigSpec relational and equal operators
|
2014-07-23 23:58:03 +02:00 |
Clifford Wolf
|
2a41afb7b2
|
Added RTLIL::SigSpec::repeat()
|
2014-07-23 21:34:14 +02:00 |
Clifford Wolf
|
c094c53de8
|
Removed RTLIL::SigSpec::optimize()
|
2014-07-23 20:32:28 +02:00 |
Clifford Wolf
|
a62c21c9c6
|
Removed RTLIL::SigSpec::expand() method
|
2014-07-23 19:34:51 +02:00 |
Clifford Wolf
|
4e802eb7f6
|
Fixed all users of SigSpec::chunks_rw() and removed it
|
2014-07-23 15:36:09 +02:00 |
Clifford Wolf
|
85db102e13
|
Replaced RTLIL::SigSpec::operator!=() with inline version
|
2014-07-23 15:35:09 +02:00 |
Clifford Wolf
|
ec923652e2
|
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
|
2014-07-23 09:52:55 +02:00 |
Clifford Wolf
|
260c19ec5a
|
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3
|
2014-07-23 09:34:47 +02:00 |
Clifford Wolf
|
c61467a32c
|
Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&)
|
2014-07-23 08:59:54 +02:00 |
Clifford Wolf
|
9e94f41b89
|
SigSpec refactoring: Added RTLIL::SigSpecIterator
|
2014-07-22 23:49:26 +02:00 |
Clifford Wolf
|
f80da7b41d
|
SigSpec refactoring: added RTLIL::SigSpec::operator[]
|
2014-07-22 22:54:03 +02:00 |
Clifford Wolf
|
a97be0828a
|
Removed RTLIL::SigChunk::compare()
|
2014-07-22 21:40:52 +02:00 |
Clifford Wolf
|
08e1e25169
|
SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api
|
2014-07-22 21:33:52 +02:00 |
Clifford Wolf
|
28b3fd05fa
|
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
|
2014-07-22 20:58:44 +02:00 |
Clifford Wolf
|
7bffde6abd
|
SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only
|
2014-07-22 20:39:38 +02:00 |
Clifford Wolf
|
4b4048bc5f
|
SigSpec refactoring: using the accessor functions everywhere
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
16e5ae0b92
|
SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and added accessor functions
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
a233762a81
|
SigSpec refactoring: renamed chunks and width to __chunks and __width
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
361e0d62ff
|
Replaced depricated NEW_WIRE macro with module->addWire() calls
|
2014-07-21 12:42:02 +02:00 |
Clifford Wolf
|
1d88f1cf9f
|
Removed deprecated module->new_wire()
|
2014-07-21 12:35:06 +02:00 |
Clifford Wolf
|
54b0f2e659
|
Added module->remove(), module->addWire(), module->addCell(), cell->check()
|
2014-07-21 12:02:55 +02:00 |
Clifford Wolf
|
e57db5e9b2
|
Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion
|
2014-07-20 11:01:04 +02:00 |
Clifford Wolf
|
efa7884026
|
Added SIZE() macro
|
2014-07-20 10:36:14 +02:00 |
Clifford Wolf
|
a721f7d768
|
Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>
|
2014-07-18 11:36:34 +02:00 |
Clifford Wolf
|
2d69c309f9
|
Added function-like cell creation helpers
|
2014-07-18 10:27:06 +02:00 |
Clifford Wolf
|
d4a1b0af5b
|
Added support for dlatchsr cells
|
2014-03-31 14:14:40 +02:00 |
Clifford Wolf
|
b7c71d92f6
|
Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API
|
2014-03-15 14:35:29 +01:00 |
Clifford Wolf
|
77e5968323
|
Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API
|
2014-03-14 11:45:44 +01:00 |
Clifford Wolf
|
fdef064b1d
|
Added RTLIL::Module::add... helper methods
|
2014-03-10 03:02:27 +01:00 |
Clifford Wolf
|
fa295a4528
|
Added generic RTLIL::SigSpec::parse_sel() with support for selection variables
|
2014-02-06 19:22:46 +01:00 |
Clifford Wolf
|
f9c4d33909
|
Added RTLIL::SigSpec::to_single_sigbit()
|
2014-02-02 21:35:26 +01:00 |
Clifford Wolf
|
651ce67d97
|
Added select -assert-none and -assert-any
|
2014-01-17 16:34:50 +01:00 |
Clifford Wolf
|
eec2cd1e78
|
Added RTLIL::SigSpec::optimized() API
|
2014-01-03 02:43:31 +01:00 |
Clifford Wolf
|
c69c416d28
|
Added $bu0 cell (for easy correct $eq/$ne mapping)
|
2013-12-28 12:02:14 +01:00 |
Clifford Wolf
|
ecc30255ba
|
Added proper === and !== support in constant expressions
|
2013-12-27 13:50:08 +01:00 |
Clifford Wolf
|
ccf083e5b0
|
Fixed uninitialized const flags bug
|
2013-12-07 16:56:34 +01:00 |
Clifford Wolf
|
f4b46ed31e
|
Replaced signed_parameters API with CONST_FLAG_SIGNED
|
2013-12-04 14:24:44 +01:00 |
Clifford Wolf
|
93a70959f3
|
Replaced RTLIL::Const::str with generic decoder method
|
2013-12-04 14:14:05 +01:00 |
Clifford Wolf
|
8dafecd34d
|
Added module->avail_parameters (for advanced techmap features)
|
2013-11-24 20:29:07 +01:00 |
Clifford Wolf
|
f71e27dbf1
|
Remove auto_wire framework (smarter than the verilog standard)
|
2013-11-24 17:29:11 +01:00 |
Clifford Wolf
|
609caa23b5
|
Implemented correct handling of signed module parameters
|
2013-11-24 17:17:21 +01:00 |
Clifford Wolf
|
532091afcb
|
Added more generic _TECHMAP_ wire mechanism to techmap pass
|
2013-11-23 15:58:06 +01:00 |
Clifford Wolf
|
8e58bb330d
|
Added SigBit struct and refactored RTLIL::SigSpec::extract
|
2013-11-22 04:07:13 +01:00 |
Clifford Wolf
|
09471846c5
|
Major improvements in mem2reg and added "init" sync rules
|
2013-11-21 13:49:00 +01:00 |
Clifford Wolf
|
223892ac28
|
Improved user-friendliness of "sat" and "eval" expression parsing
|
2013-11-09 12:02:27 +01:00 |
Clifford Wolf
|
947bd9b96b
|
Renamed extend_un0() to extend_u0() and use it in genrtlil
|
2013-11-07 18:17:10 +01:00 |
Clifford Wolf
|
0e1661f84e
|
Fixed type of sign extension in opt_const $eq/$ne handling
|
2013-11-07 16:53:28 +01:00 |
Clifford Wolf
|
bd2c8ec886
|
Added design->full_selection() helper method
|
2013-10-27 09:30:58 +01:00 |
Clifford Wolf
|
e679a5d046
|
Fixed handling of boolean attributes (passes)
|
2013-10-24 11:37:54 +02:00 |
Clifford Wolf
|
eae43e2db4
|
Fixed handling of boolean attributes (kernel)
|
2013-10-24 10:59:27 +02:00 |
Clifford Wolf
|
8e8f1994b8
|
Changed NEW_WIRE API to return the wire, not the signal
|
2013-10-18 14:19:45 +02:00 |
Clifford Wolf
|
cc5e379eca
|
Added RTLIL NEW_WIRE macro
|
2013-10-18 13:25:24 +02:00 |
Clifford Wolf
|
376150c926
|
Added techmap -opt mode
|
2013-08-09 15:20:22 +02:00 |
Clifford Wolf
|
05483619f0
|
Some fixes to improve determinism
|
2013-08-09 12:42:32 +02:00 |
Clifford Wolf
|
0f38008ed3
|
Added "design" command (-reset, -save, -load)
|
2013-07-27 14:27:51 +02:00 |
Clifford Wolf
|
21e38bed98
|
Added "eval" pass
|
2013-06-19 09:30:37 +02:00 |
Clifford Wolf
|
a046a302f0
|
Fixed build with clang
|
2013-06-18 19:54:33 +02:00 |
Clifford Wolf
|
6971c4db62
|
Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API
|
2013-06-18 17:11:13 +02:00 |
Clifford Wolf
|
21d9251e52
|
Added "dump" command (part ilang backend)
|
2013-06-02 17:53:30 +02:00 |
Clifford Wolf
|
88af5b6a16
|
Improved opt_share for reduce cells
|
2013-03-29 11:19:21 +01:00 |
Clifford Wolf
|
d4680fd5a0
|
Added design->select() api and use it in extract pass
|
2013-03-03 20:53:24 +01:00 |
Clifford Wolf
|
1bc0f04789
|
Added id2cstr API
|
2013-03-01 09:01:49 +01:00 |
Clifford Wolf
|
51c2b797b3
|
Do not unescape identifiers starting with \$
|
2013-03-01 01:10:11 +01:00 |
Clifford Wolf
|
7764d0ba1d
|
initial import
|
2013-01-05 11:13:26 +01:00 |