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4 Commits

Author SHA1 Message Date
Icenowy Zheng d53a2bd1d3 anlogic: add support for Eagle Distributed RAM 
The MSLICEs on the Eagle series of FPGA can be configured as Distributed
RAM.

Enable to synthesis to DRAM.

As the Anlogic software suite doesn't support any 'bx to exist in the
initializtion data of DRAM, do not enable the initialization support of
the inferred DRAM.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2018-12-17 23:20:40 +08:00
Icenowy Zheng 634d7d1c14 Revert "Leave only real black box cells" 
This reverts commit 43030db5ff.

For a synthesis tool, generating EG_LOGIC cells are a good choice, as
they can be furtherly optimized when PnR, although sometimes EG_LOGIC is
not as blackbox as EG_PHY cells (because the latter is more close to the
hardware implementation).

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2018-12-17 23:20:40 +08:00
Miodrag Milanovic 43030db5ff Leave only real black box cells 2018-12-02 11:57:50 +01:00
Miodrag Milanovic 83bce9f59c Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00