Eddie Hung
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d0ffe7544c
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Canonical form
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2019-08-22 08:05:01 -07:00 |
Clifford Wolf
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34a7c0209d
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Merge pull request #1316 from YosysHQ/eddie/fix_mem2reg
mem2reg to preserve user attributes and src
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2019-08-22 10:24:42 +02:00 |
Eddie Hung
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bb1a8a0190
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Add test
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2019-08-21 21:58:20 -07:00 |
Eddie Hung
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d3a212ff91
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opt_expr to trim A port of $shiftx if Y_WIDTH == 1
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2019-08-21 21:53:55 -07:00 |
Eddie Hung
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7d02d17b16
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Reuse var
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2019-08-21 19:18:40 -07:00 |
Eddie Hung
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5c8344363f
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Revert "Trim shiftx_width when upper bits are 1'bx"
This reverts commit 7e7965ca7b .
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2019-08-21 19:18:27 -07:00 |
Eddie Hung
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c7859531c2
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opt_expr to trim A port of $shiftx if Y_WIDTH == 1
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2019-08-21 19:18:05 -07:00 |
Eddie Hung
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7e7965ca7b
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Trim shiftx_width when upper bits are 1'bx
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2019-08-21 18:43:17 -07:00 |
Eddie Hung
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ed7be3e6b6
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Add comment
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2019-08-21 17:36:38 -07:00 |
Eddie Hung
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15188033da
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Add variable length support to xilinx_srl
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2019-08-21 17:34:40 -07:00 |
Eddie Hung
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6d76ae4c65
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Rename pattern to fixed
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2019-08-21 15:46:58 -07:00 |
Eddie Hung
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b0a3b430bf
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attribute -> attr
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2019-08-21 15:44:07 -07:00 |
Eddie Hung
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61b4d7ae13
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Use Cell::has_keep_attribute()
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2019-08-21 15:41:46 -07:00 |
Eddie Hung
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edec73fec1
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abc9 to perform new 'map_ffs' before 'map_luts'
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2019-08-21 15:37:55 -07:00 |
Eddie Hung
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6fa9e03e4c
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xilinx_srl to support FDRE and FDRE_1
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2019-08-21 15:35:29 -07:00 |
Eddie Hung
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3c8e8521a6
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Fix polarity of EN_POL
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2019-08-21 14:42:11 -07:00 |
whitequark
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841903582f
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Merge pull request #1315 from mmicko/fix_dependencies
Fix test_pmgen deps
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2019-08-21 21:40:31 +00:00 |
Eddie Hung
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a980f0d4be
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Add CLKPOL == 0
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2019-08-21 14:35:40 -07:00 |
Eddie Hung
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1c7d721558
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Reject if not minlen from inside pattern matcher
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2019-08-21 14:26:24 -07:00 |
Eddie Hung
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cab2bd083e
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Get wire via SigBit
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2019-08-21 13:47:47 -07:00 |
Eddie Hung
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52fea5b658
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Respect \keep on cells or wires
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2019-08-21 13:42:03 -07:00 |
Eddie Hung
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b808123e71
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Merge branch 'eddie/fix_mem2reg' into eddie/xilinx_srl
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2019-08-21 13:37:45 -07:00 |
Eddie Hung
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a6776ee35e
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mem2reg to preserve user attributes and src
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2019-08-21 13:36:01 -07:00 |
Eddie Hung
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5ce0c31d0e
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Add init support
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2019-08-21 13:05:10 -07:00 |
Eddie Hung
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df53fe12e7
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Fix spacing
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2019-08-21 12:54:11 -07:00 |
Eddie Hung
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0250712486
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Initial progress on xilinx_srl
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2019-08-21 12:50:49 -07:00 |
SergeyDegtyar
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d945b8a357
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Fix all comments from PR
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2019-08-21 21:52:07 +03:00 |
Eddie Hung
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c7af71ecde
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Use semicolon
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2019-08-21 11:47:17 -07:00 |
Eddie Hung
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5d0f6cbd54
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techmap before read
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2019-08-21 11:47:06 -07:00 |
Eddie Hung
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d4d692989a
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Merge remote-tracking branch 'origin/master' into xaig_arrival
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2019-08-21 11:39:20 -07:00 |
Eddie Hung
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8f69be9cc7
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Merge remote-tracking branch 'origin/master' into xaig_arrival
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2019-08-21 11:39:14 -07:00 |
Eddie Hung
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399ac760ff
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Output "h" extension only if boxes
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2019-08-21 11:31:18 -07:00 |
Eddie Hung
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8f0c1232d7
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Revert "Fix omode which inserts an output if none exists (otherwise abc9 breaks)"
This reverts commit 8182cb9d91 .
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2019-08-21 11:29:40 -07:00 |
Eddie Hung
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584c680691
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Add abc_arrival to SRL*
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2019-08-21 11:27:42 -07:00 |
Miodrag Milanovic
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948b6f91a1
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Fix test_pmgen deps
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2019-08-21 17:00:24 +02:00 |
Clifford Wolf
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7d8db1c053
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Merge pull request #1314 from YosysHQ/eddie/fix_techmap
techmap -max_iter to apply to each module individually
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2019-08-21 09:12:56 +02:00 |
SergeyDegtyar
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b835ec37cb
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Add temp directory
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2019-08-21 07:53:34 +03:00 |
Eddie Hung
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8182cb9d91
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Fix omode which inserts an output if none exists (otherwise abc9 breaks)
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2019-08-20 21:30:16 -07:00 |
Eddie Hung
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4d123b7638
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Revert "Only xaig if GetSize(output_bits) > 0"
This reverts commit 7b646101e9 .
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2019-08-20 21:22:38 -07:00 |
Eddie Hung
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7b646101e9
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Only xaig if GetSize(output_bits) > 0
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2019-08-20 20:57:13 -07:00 |
Eddie Hung
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076af2e617
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Missing newline
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2019-08-20 20:37:52 -07:00 |
Eddie Hung
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4cc74346f1
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Fix compile error
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2019-08-20 20:27:05 -07:00 |
Eddie Hung
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9b9d759451
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Fix copy-paste typo
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2019-08-20 20:18:51 -07:00 |
Eddie Hung
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b7a48e3e0f
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Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-08-20 20:18:17 -07:00 |
Eddie Hung
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64d62710de
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Oops
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2019-08-20 20:07:38 -07:00 |
Eddie Hung
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affe9c9c1a
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Merge branch 'eddie/fix_techmap' into xaig_arrival
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2019-08-20 20:06:47 -07:00 |
Eddie Hung
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fe61dcce8b
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Grammar
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2019-08-20 20:05:51 -07:00 |
Eddie Hung
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fce8dc7db2
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Add test
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2019-08-20 20:05:16 -07:00 |
Eddie Hung
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193eae0c84
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techmap -max_iter to apply to each module individually
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2019-08-20 19:50:20 -07:00 |
Eddie Hung
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57493e328a
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techmap -max_iter to apply to each module individually
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2019-08-20 19:48:16 -07:00 |