Eddie Hung
6e475484b2
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-30 09:37:32 -07:00
David Shah
6919c0f9b0
Merge branch 'master' into xc7dsp
2019-08-30 13:57:15 +01:00
Eddie Hung
1b08f861b6
Merge branch 'eddie/xilinx_srl' into xaig_arrival
2019-08-28 15:31:48 -07:00
Eddie Hung
8d820a9884
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-28 15:19:10 -07:00
Eddie Hung
9314a0a42e
Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor
2019-08-28 10:51:39 -07:00
Eddie Hung
ba5d81c7f1
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-28 09:21:03 -07:00
Marcin Kościelnicki
d361f5ab79
xilinx: Add SRLC16E primitive.
...
Fixes #1331 .
2019-08-27 20:27:12 +02:00
Eddie Hung
1ba09c4ab7
Merge branch 'master' into eddie/xilinx_srl
2019-08-26 13:56:31 -07:00
Eddie Hung
a098205479
Merge branch 'master' into mwk/xilinx_bufgmap
2019-08-26 13:25:17 -07:00
Eddie Hung
d7051b90de
Add undocumented feature
2019-08-23 16:41:32 -07:00
Eddie Hung
08139aa53a
xilinx_srl now copes with word-level flops $dff{,e}
2019-08-23 12:22:46 -07:00
Eddie Hung
78b7d8f531
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-23 11:32:44 -07:00
Eddie Hung
e658d472c8
Put attributes above port
2019-08-23 11:31:20 -07:00
Eddie Hung
d672b1ddec
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-23 11:26:55 -07:00
Eddie Hung
20f4d191b5
Merge branch 'master' into mwk/xilinx_bufgmap
2019-08-23 11:24:19 -07:00
Eddie Hung
509c353fe9
Forgot one
2019-08-23 11:23:50 -07:00
Eddie Hung
0d0ad15898
Merge branch 'master' into mwk/xilinx_bufgmap
2019-08-23 11:23:31 -07:00
Eddie Hung
a270af00cc
Put abc_* attributes above port
2019-08-23 11:21:44 -07:00
Eddie Hung
6872805a3e
Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
2019-08-23 10:00:50 -07:00
Eddie Hung
15188033da
Add variable length support to xilinx_srl
2019-08-21 17:34:40 -07:00
Eddie Hung
edec73fec1
abc9 to perform new 'map_ffs' before 'map_luts'
2019-08-21 15:37:55 -07:00
Eddie Hung
5ce0c31d0e
Add init support
2019-08-21 13:05:10 -07:00
Eddie Hung
c7af71ecde
Use semicolon
2019-08-21 11:47:17 -07:00
Eddie Hung
5d0f6cbd54
techmap before read
2019-08-21 11:47:06 -07:00
Eddie Hung
584c680691
Add abc_arrival to SRL*
2019-08-21 11:27:42 -07:00
Eddie Hung
b7a48e3e0f
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-20 20:18:17 -07:00
Eddie Hung
64d62710de
Oops
2019-08-20 20:07:38 -07:00
Eddie Hung
c26c556384
xilinx to use abc_map.v with -max_iter 1
2019-08-20 19:47:11 -07:00
Eddie Hung
343039496b
Add reference to FD* timing
2019-08-20 18:22:58 -07:00
Eddie Hung
f1a206ba03
Revert "Remove sequential extension"
...
This reverts commit 091bf4a18b
.
2019-08-20 18:17:14 -07:00
Eddie Hung
091bf4a18b
Remove sequential extension
2019-08-20 18:16:37 -07:00
Eddie Hung
bbab608691
Remove SRL* delays from cells_sim.v
2019-08-20 18:14:40 -07:00
Eddie Hung
aa2d3af631
LUTMUX -> LUTMUX6
2019-08-20 18:08:07 -07:00
Eddie Hung
30a379b5b6
Cleanup techmap in map_luts
2019-08-20 17:59:31 -07:00
Eddie Hung
3b52d6e29c
Move `techmap abc_map.v` into map_luts
2019-08-20 17:55:12 -07:00
Eddie Hung
54284aaa98
Remove delays from abc_map.v
2019-08-20 17:52:27 -07:00
Eddie Hung
96f00e9147
Typo
2019-08-20 17:51:50 -07:00
Eddie Hung
8f666ebac1
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-20 17:36:14 -07:00
Eddie Hung
e273ed5275
Wrap SRL{16,32} too
2019-08-20 15:09:38 -07:00
Eddie Hung
808f07630f
Wrap LUTRAMs in order to capture comb/seq behaviour
2019-08-20 14:49:11 -07:00
Eddie Hung
0079e9b4a6
Add LUTRAM delays
2019-08-20 13:53:38 -07:00
Eddie Hung
8d0cffaf20
Remove mapping rules
2019-08-20 13:11:39 -07:00
Eddie Hung
33960dd3d8
Merge pull request #1209 from YosysHQ/eddie/synth_xilinx
...
[WIP] synth xilinx renaming, as per #1184
2019-08-20 12:55:26 -07:00
Eddie Hung
5eda5fc7eb
Remove -icells
2019-08-20 12:41:11 -07:00
Eddie Hung
be9e4f1b67
Use abc_{map,unmap,model}.v
2019-08-20 12:39:11 -07:00
Eddie Hung
c4d4c6db3f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-20 12:00:12 -07:00
Eddie Hung
d9fe4cccbf
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx
2019-08-20 11:57:52 -07:00
Eddie Hung
526e081342
Add arrival times for SRL outputs
2019-08-19 15:15:43 -07:00
Eddie Hung
b71212ddea
Add BRAM arrival times
2019-08-19 12:46:35 -07:00
Eddie Hung
2f86366087
Add reference to source of Tclktoq timing
2019-08-19 12:39:22 -07:00
Eddie Hung
d02ef8c73f
Add 'abc_arrival' attribute for flop outputs
2019-08-19 11:32:18 -07:00
Eddie Hung
f25837f8e8
Update box timings
2019-08-19 11:31:40 -07:00
Eddie Hung
ba2261e21a
Move from cell attr to module attr
2019-08-19 11:18:33 -07:00
Eddie Hung
d81a090d89
Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro
2019-08-19 09:56:17 -07:00
Eddie Hung
e301440a0b
Use attributes instead of params
2019-08-19 09:51:49 -07:00
Eddie Hung
24c934f1af
Merge branch 'eddie/abc9_refactor' into xaig_dff
2019-08-16 16:51:22 -07:00
Eddie Hung
562c9e3624
Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules
2019-08-16 15:40:53 -07:00
Eddie Hung
261daffd9d
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
2019-08-15 12:19:47 -07:00
Marcin Kościelnicki
3c75a72feb
move attributes to wires
2019-08-13 19:36:59 +00:00
Eddie Hung
ed4b2834ef
Add assign PCOUT = P to DSP48E1
2019-08-13 12:19:26 -07:00
Marcin Kościelnicki
49765ec19e
minor review fixes
2019-08-13 18:05:49 +00:00
Eddie Hung
2a1b98d478
Add DSP_A_MAXWIDTH_PARTIAL, refactor
2019-08-13 10:21:24 -07:00
David Shah
edff79a25a
xilinx: Rework labels for faster Verilator testing
...
Signed-off-by: David Shah <dave@ds0.me>
2019-08-13 10:29:42 +01:00
Marcin Kościelnicki
c6d5b97b98
review fixes
2019-08-13 00:35:54 +00:00
Marcin Kościelnicki
f4c62f33ac
Add clock buffer insertion pass, improve iopadmap.
...
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-13 00:16:38 +02:00
Eddie Hung
f890cfb63b
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-12 11:32:10 -07:00
Eddie Hung
0b5b56c1ec
Pack partial-product adder DSP48E1 packing
2019-08-09 15:19:33 -07:00
Eddie Hung
1f722b3500
Remove signed from ports in +/xilinx/dsp_map.v
2019-08-08 16:33:20 -07:00
Eddie Hung
162eab6b74
Combine techmap calls
2019-08-08 10:55:48 -07:00
Eddie Hung
7160243874
Move xilinx_dsp to before alumacc
2019-08-08 10:45:56 -07:00
Eddie Hung
57b2e4b9c1
INMODE is 5 bits
2019-08-08 10:44:35 -07:00
Eddie Hung
13cc106cf7
Fix copy-pasta typo
2019-08-08 10:44:26 -07:00
David Shah
b8cd4ad64a
DSP48E1 sim model: add SIMD tests
...
Signed-off-by: David Shah <dave@ds0.me>
2019-08-08 11:39:35 +01:00
David Shah
57aeb4cc01
DSP48E1 model: test CE inputs
...
Signed-off-by: David Shah <dave@ds0.me>
2019-08-08 11:32:43 +01:00
David Shah
d60b3c0dc8
DSP48E1 sim model: fix seq tests and add preadder tests
...
Signed-off-by: David Shah <dave@ds0.me>
2019-08-08 11:18:37 +01:00
David Shah
e7dbe7bb3d
DSP48E1 sim model: seq test working
...
Signed-off-by: David Shah <dave@ds0.me>
2019-08-08 10:52:04 +01:00
David Shah
f6605c7dc0
DSP48E1 sim model: Comb, no pre-adder, mode working
...
Signed-off-by: David Shah <dave@ds0.me>
2019-08-08 10:26:44 +01:00
David Shah
f0f352e971
[wip] sim model testing
...
Signed-off-by: David Shah <dave@ds0.me>
2019-08-08 10:05:11 +01:00
David Shah
ccfb4ff2a9
[wip] sim model testing
...
Signed-off-by: David Shah <dave@ds0.me>
2019-08-08 09:31:34 +01:00
Eddie Hung
48d0f99406
stoi -> atoi
2019-08-07 11:09:17 -07:00
David Shah
fe95807f16
[wip] DSP48E1 sim model improvements
...
Signed-off-by: David Shah <dave@ds0.me>
2019-08-07 13:09:12 +01:00
David Shah
c43b0c4b49
[wip] DSP48E1 sim model improvements
...
Signed-off-by: David Shah <dave@ds0.me>
2019-08-06 18:47:18 +01:00
David Shah
7a563d0b92
[wip] DSP48E1 sim model improvements
...
Signed-off-by: David Shah <dave@ds0.me>
2019-08-06 13:23:42 +01:00
Eddie Hung
fc0b5d5ab6
Change $__softmul back to $mul
2019-08-01 12:45:14 -07:00
Eddie Hung
ed303b07b7
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-01 12:02:16 -07:00
Eddie Hung
66806085db
RST -> RSTBRST for RAMB8BWER
2019-07-29 16:05:44 -07:00
David Shah
ab607e896e
xilinx: Fix missing cell name underscore in cells_map.v
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-25 08:19:07 +01:00
Eddie Hung
601fac97e4
Add params
2019-07-18 21:02:49 -07:00
Eddie Hung
43616e1414
Update Makefile too
2019-07-18 14:51:55 -07:00
Eddie Hung
b97fe6e866
Work in progress for renaming labels/options in synth_xilinx
2019-07-18 14:20:43 -07:00
Eddie Hung
5562cb08a4
Use single DSP_SIGNEDONLY macro
2019-07-18 13:09:55 -07:00
Eddie Hung
e3f8e59f18
Make all operands signed
2019-07-17 14:25:40 -07:00
Eddie Hung
58e63feae1
Update comment
2019-07-17 13:26:17 -07:00
Eddie Hung
c501aa5ee8
Signedness
2019-07-16 15:54:27 -07:00
Eddie Hung
6390c535ba
Revert drop down to 24x16 multipliers for all
2019-07-16 14:30:25 -07:00
Eddie Hung
569cd66764
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
2019-07-16 14:18:36 -07:00
Eddie Hung
5d1ce04381
Add support for {A,B,P}REG in DSP48E1
2019-07-16 14:05:50 -07:00
David Shah
d38df68d26
xilinx: Add correct signed behaviour to DSP48E1 model
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-16 17:53:08 +01:00
David Shah
95c8d27b0b
xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed)
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-16 16:47:53 +01:00
Eddie Hung
5f00d335d4
Oops forgot these files
2019-07-15 15:03:15 -07:00
Eddie Hung
0c7ee6d0fa
Move DSP mapping back out to dsp_map.v
2019-07-15 14:18:44 -07:00
Eddie Hung
20e3d2d9b0
Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim
2019-07-15 11:13:22 -07:00
Eddie Hung
146451a767
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-07-15 09:49:41 -07:00
Eddie Hung
1c9f3fadb9
Add Tsu offset to boxes, and comments
2019-07-11 17:17:26 -07:00
Eddie Hung
d386177e6d
ABC doesn't like negative delays in flop boxes...
2019-07-11 17:09:17 -07:00
Eddie Hung
3ef927647c
Fix FDCE_1 box
2019-07-11 14:25:47 -07:00
Eddie Hung
1ada568134
Revert "$pastQ should be first input"
...
This reverts commit 8f9d529929
.
2019-07-11 14:23:45 -07:00
Eddie Hung
854333f2af
Propagate INIT attr
2019-07-11 13:55:47 -07:00
Eddie Hung
8f9d529929
$pastQ should be first input
2019-07-11 13:54:40 -07:00
Eddie Hung
021f8e5492
Fix typo
2019-07-11 13:23:07 -07:00
Eddie Hung
19c1c3cfa3
Merge pull request #1182 from koriakin/xc6s-bram
...
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 12:55:35 -07:00
Marcin Kościelnicki
a9efacd01d
xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.
2019-07-11 21:13:12 +02:00
Eddie Hung
8fef4c3594
Simplify to $__ABC_ASYNC box
2019-07-11 10:52:33 -07:00
Eddie Hung
93fbd56db1
$__ABC_FD_ASYNC_MUX.Q -> Y
2019-07-11 10:25:59 -07:00
Marcin Kościelnicki
ce250b341c
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
Eddie Hung
d357431df1
Restore from master
2019-07-10 22:54:39 -07:00
Eddie Hung
f984e0cb34
Another typo
2019-07-10 22:33:35 -07:00
Eddie Hung
ea6ffea2cd
Fix clk_pol for FD*_1
2019-07-10 20:10:20 -07:00
Eddie Hung
7899a06ed6
Another typo
2019-07-10 19:59:24 -07:00
Eddie Hung
ad35b509de
Another typo
2019-07-10 19:05:53 -07:00
Eddie Hung
f3511e4f93
Use \$currQ
2019-07-10 19:01:13 -07:00
Eddie Hung
f030be3f1c
Preserve all parameters, plus some extra ones for clk/en polarity
2019-07-10 18:57:11 -07:00
Eddie Hung
4a995c5d80
Change how to specify flops to ABC again
2019-07-10 17:54:56 -07:00
Eddie Hung
3bb48facb2
Remove params from FD*_1 variants
2019-07-10 17:17:54 -07:00
Eddie Hung
0372c900e8
Fix typo, and have !{PRE,CLR} behave as CE
2019-07-10 17:15:49 -07:00
Eddie Hung
7b2599cb94
Move ABC FF stuff to abc_ff.v; add support for other FD* types
2019-07-10 17:06:05 -07:00
Eddie Hung
0ab8f28bc7
Uncomment IS_C_INVERTED parameter
2019-07-10 16:23:15 -07:00
Eddie Hung
838ae1a14c
synth_xilinx's map_cells stage to techmap ff_map.v
2019-07-10 16:15:57 -07:00
Eddie Hung
73c8f1a59e
Fix box numbering
2019-07-10 16:12:33 -07:00
Eddie Hung
052060f109
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-10 16:05:41 -07:00
Eddie Hung
b33ecd2a74
Move dsp_map.v into cells_map.v; cleanup synth_xilinx a little
2019-07-10 16:00:03 -07:00
Eddie Hung
cea7441d8a
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-07-10 15:58:01 -07:00
Eddie Hung
bb2144ae73
Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime
...
Error out if -abc9 and -retime specified
2019-07-10 14:38:13 -07:00
Eddie Hung
6bbd286e03
Error out if -abc9 and -retime specified
2019-07-10 12:47:48 -07:00
Eddie Hung
58bb84e5b2
Add some spacing
2019-07-10 12:32:33 -07:00
Eddie Hung
521971e32e
Add some ASCII art explaining mux decomposition
2019-07-10 12:20:04 -07:00
Eddie Hung
e573d024a2
Call muxpack and pmux2shiftx before cmp2lut
2019-07-09 21:26:38 -07:00
Eddie Hung
c55530b901
Restore opt_clean back to original place
2019-07-09 14:29:58 -07:00
Eddie Hung
5b48b18d29
Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6
2019-07-09 14:28:54 -07:00
Eddie Hung
b1a048a703
Extend using A[1] to preserve don't care
2019-07-09 12:35:41 -07:00
Eddie Hung
93522b0ae1
Extend during mux decomposition with 1'bx
2019-07-09 10:59:37 -07:00
Eddie Hung
c864995343
Fix typo and comments
2019-07-09 10:38:07 -07:00
Eddie Hung
c91cb73562
Merge remote-tracking branch 'origin/master' into xc7mux
2019-07-09 10:22:49 -07:00
Eddie Hung
c68b909210
synth_xilinx to call commands of synth -coarse directly
2019-07-09 10:21:54 -07:00
Eddie Hung
737340327f
Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""
...
This reverts commit 7f964859ec
.
2019-07-09 10:15:02 -07:00
Eddie Hung
bc84f7dd10
Fix spacing
2019-07-09 09:22:12 -07:00
Eddie Hung
667199d460
Fix spacing
2019-07-09 09:16:00 -07:00
Eddie Hung
6951e32070
Decompose mux inputs in delay-orientated (rather than area) fashion
2019-07-08 23:51:13 -07:00
Eddie Hung
45da3ada7b
Do not call opt -mux_undef (part of -full) before muxcover
2019-07-08 23:49:16 -07:00
Eddie Hung
d4ab43d940
Add one more comment
2019-07-08 23:05:48 -07:00
Eddie Hung
939a225f92
Less thinking
2019-07-08 23:02:57 -07:00
Eddie Hung
de40453553
Reword
2019-07-08 22:56:19 -07:00
Eddie Hung
7f964859ec
synth_xilinx to call "synth -run coarse" with "-keepdc"
2019-07-08 19:23:24 -07:00
Eddie Hung
3f86407cc3
Map $__XILINX_SHIFTX in a more balanced manner
2019-07-08 17:06:35 -07:00
Eddie Hung
78914e2e0e
Capitalisation
2019-07-08 17:06:22 -07:00
Eddie Hung
baf47e496f
Add synth_xilinx -widemux recommended value
2019-07-08 17:04:39 -07:00
Eddie Hung
895ca50173
Fixes for 2:1 muxes
2019-07-08 12:03:38 -07:00
Eddie Hung
0944acf3af
synth_xilinx -widemux=2 is minimum now
2019-07-08 11:29:21 -07:00
David Shah
c865559f95
xc7: Map combinational DSP48E1s
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-08 19:15:25 +01:00
Eddie Hung
dbe1326573
Parametric muxcover costs as per @daveshah1
2019-07-08 11:08:20 -07:00
Eddie Hung
c58998a7d2
atoi -> stoi as per @daveshah1
2019-07-08 10:48:10 -07:00
Eddie Hung
810f8c5dbd
Merge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanup
2019-07-02 09:21:02 -07:00
Eddie Hung
2ea6083b7e
Fix $__XILINX_MUXF78 box timing
2019-07-01 14:04:06 -07:00
Eddie Hung
09ac274716
Revert "Fix broken MUXFx box, use MUXF7x2 box instead"
...
This reverts commit a9a140aa6c
.
2019-07-01 14:01:09 -07:00
Eddie Hung
a9a140aa6c
Fix broken MUXFx box, use MUXF7x2 box instead
2019-07-01 13:36:27 -07:00
Eddie Hung
5466121ffb
Capture all data in one "abc_flop" attribute
2019-07-01 11:50:14 -07:00
Eddie Hung
659c04a68d
Update abc_box_id numbering
2019-07-01 10:47:14 -07:00
Eddie Hung
699d8e3939
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-01 10:44:42 -07:00
Eddie Hung
85f1c2dcbe
Cleanup SRL inference/make more consistent
2019-06-29 21:42:20 -07:00
Eddie Hung
62ba724ccb
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-29 19:39:27 -07:00
Eddie Hung
dd8d264bf5
install *_nowide.lut files
2019-06-29 19:37:04 -07:00
Eddie Hung
728839d6ca
Remove peepopt call in synth_xilinx since already in synth -run coarse
2019-06-28 12:53:38 -07:00
Eddie Hung
ea0f7c9be9
Restore $__XILINX_MUXF78 const optimisation
2019-06-28 12:12:41 -07:00
Eddie Hung
a193bf27c9
Clean up trimming leading 1'bx in A during techmappnig
2019-06-28 12:03:43 -07:00
Eddie Hung
cf020befeb
Fix CARRY4 abc_box_id
2019-06-28 11:28:50 -07:00
Eddie Hung
4ef26d4755
Merge remote-tracking branch 'origin/master' into xc7mux
2019-06-28 11:09:42 -07:00
Eddie Hung
00f63d82ce
Reduce diff with upstream
2019-06-27 16:13:22 -07:00
Eddie Hung
9398921af1
Refactor for one "abc_carry" attribute on module
2019-06-27 16:07:14 -07:00
Eddie Hung
312c03e4ca
Remove redundant doc
2019-06-27 15:28:55 -07:00
Eddie Hung
4d00e27ed7
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-27 11:23:30 -07:00
Eddie Hung
1237a4c116
Add warning if synth_xilinx -abc9 with family != xc7
2019-06-27 11:22:49 -07:00
Eddie Hung
6c256b8cda
Merge origin/master
2019-06-27 11:20:15 -07:00
Eddie Hung
593e4a30bb
MUXF78 -> $__MUXF78 to indicate internal
2019-06-26 20:09:28 -07:00
Eddie Hung
dbb8c8caaa
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-26 20:07:31 -07:00
Eddie Hung
a7a88109f5
Update comment on boxes
2019-06-26 20:00:15 -07:00
Eddie Hung
b7bef15b16
Add "WE" to dist RAM's abc_scc_break
2019-06-26 19:58:09 -07:00
Eddie Hung
b9ff0503f3
synth_xilinx's muxcover call to be very conservative -- -nodecode
2019-06-26 17:57:10 -07:00
Eddie Hung
f0a1726a1a
Accidentally removed "simplemap $mux"
2019-06-26 17:48:49 -07:00
Eddie Hung
2b104ed6c8
Replace with <internal options>
2019-06-26 17:42:50 -07:00
Eddie Hung
cae69a3edd
Rework help_mode for synth_xilinx -widemux
2019-06-26 17:41:21 -07:00
Eddie Hung
5f807a7a5b
Return to upstream synth_xilinx with opt -full and wreduce
2019-06-26 16:25:48 -07:00
Eddie Hung
812469aaa3
Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux
2019-06-26 14:48:35 -07:00
Eddie Hung
c762be5930
Instead of blocking wreduce on $mux, use -keepdc instead #1132
2019-06-26 11:48:35 -07:00
Eddie Hung
8d8261c71f
Do not call opt with -full before muxcover
2019-06-26 11:38:28 -07:00
Eddie Hung
80de03a7a6
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-26 11:24:39 -07:00
Eddie Hung
4d0014d1b1
Cleanup abc_box_id
2019-06-26 11:23:57 -07:00
Eddie Hung
612083a807
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-26 10:33:54 -07:00
Eddie Hung
5e1b8d458b
Remove unused var
2019-06-26 10:33:07 -07:00
Eddie Hung
988e6163ab
Add _nowide variants of LUT libraries in -nowidelut flows
2019-06-26 10:23:29 -07:00
Eddie Hung
799b18263f
Merge branch 'koriakin/xc7nocarrymux' into xaig
2019-06-26 10:04:01 -07:00
Miodrag Milanovic
ea0b6258ab
Simulation model verilog fix
2019-06-26 18:34:34 +02:00
Eddie Hung
7389b043c0
Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriakin/xc7nocarrymux
2019-06-26 09:33:38 -07:00
Eddie Hung
177c26ca35
Rename -minmuxf to -widemux
2019-06-26 09:16:45 -07:00
Eddie Hung
480a04cb3c
Realistic delays for RAM32X1D too
2019-06-25 09:34:28 -07:00
Eddie Hung
6095357390
Add RAM32X1D box info
2019-06-25 09:34:19 -07:00
Eddie Hung
6f36ec8ecf
Merge remote-tracking branch 'origin/master' into xaig
2019-06-25 09:33:11 -07:00
Eddie Hung
4238feed81
This optimisation doesn't seem to work...
2019-06-25 09:21:46 -07:00
Eddie Hung
158325956e
Realistic delays for RAM32X1D too
2019-06-24 23:05:28 -07:00
Eddie Hung
3825068a75
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-24 23:04:25 -07:00
Eddie Hung
2f770b7400
Use LUT delays for dist RAM delays
2019-06-24 23:02:53 -07:00
Eddie Hung
e1ba25d79f
Add RAM32X1D box info
2019-06-24 22:54:35 -07:00
Eddie Hung
1564eb8b54
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-24 22:48:49 -07:00
Eddie Hung
152e682bd5
Add Xilinx dist RAM as comb boxes
2019-06-24 21:54:01 -07:00
Eddie Hung
f1675b88f6
Merge remote-tracking branch 'origin/eddie/ram32x1d' into xc7mux
2019-06-24 16:39:18 -07:00
Eddie Hung
efd04880db
Add RAM32X1D support
2019-06-24 16:16:50 -07:00
Eddie Hung
c3df895bf4
Reduce MuxFx resources in mux techmapping
2019-06-24 15:16:44 -07:00
Eddie Hung
db6a0b72b2
Reduce number of decomposed muxes during techmap
2019-06-24 14:28:56 -07:00
Eddie Hung
2e7992efff
Revert "Fix techmapping muxes some more"
...
This reverts commit 0aae3b4f43
.
2019-06-24 14:15:31 -07:00
Eddie Hung
7fbfcf20d1
Move comment
2019-06-24 14:15:00 -07:00
Eddie Hung
0aae3b4f43
Fix techmapping muxes some more
2019-06-24 12:50:48 -07:00
Eddie Hung
2b4501503d
Fix mux techmapping
2019-06-24 12:18:17 -07:00
Eddie Hung
aa1eeda567
Modify costs for muxcover
2019-06-24 11:51:55 -07:00
Eddie Hung
36e6da5396
Change synth_xilinx's -nomux to -minmuxf <int>
2019-06-24 10:04:01 -07:00
Eddie Hung
d54dceb547
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-22 19:44:17 -07:00
Eddie Hung
792d0670c3
Add comment to xc7 box
2019-06-22 14:28:24 -07:00
Eddie Hung
7903ebe3e0
Carry in/out box ordering now move to end, not swap with end
2019-06-22 14:18:42 -07:00
Eddie Hung
65c022c257
Remove DFF and RAMD box info for now
2019-06-21 20:41:14 -07:00
Eddie Hung
bbf3ad90f5
Remove $_MUX4_ techmap rule
2019-06-21 18:12:33 -07:00
Eddie Hung
39e0e006d5
Fix wreduce call (!!!), tweak muxcover costs
2019-06-21 18:12:07 -07:00
Eddie Hung
faa2d6fc1c
Constrain wreduce only if wide mux
2019-06-21 17:12:34 -07:00
Eddie Hung
aeee9dcad7
Simplify and comment out mux_map.v
2019-06-21 17:06:30 -07:00
Eddie Hung
ed00823b41
synth_xilinx to now wreduce except $mux, remove extra peepopt
2019-06-21 16:56:56 -07:00
Eddie Hung
29aee0989f
mux_map to no longer copy last value into 1'bx
2019-06-21 16:55:59 -07:00
Eddie Hung
8bce3fb329
Fix spacing
2019-06-21 16:55:34 -07:00
Eddie Hung
694d40719f
Fix spacing again, A_forward -> A_backward
2019-06-21 16:47:07 -07:00
Eddie Hung
11886c874c
Restore wreduce to synth_xilinx, after muxcover
2019-06-21 16:18:29 -07:00
Eddie Hung
44fc616fc7
Revert B_SIGNED optimisation, since only works for Y_WIDTH==1
2019-06-21 16:18:14 -07:00
Eddie Hung
4d6fac019a
Fix spacing
2019-06-21 16:06:13 -07:00
Eddie Hung
aa0b107afb
synth_xilinx to use _ABC macro, and perform muxpack again
2019-06-21 15:48:20 -07:00
Eddie Hung
9abde12110
Add $__XILINX_MUXF78 to preserve entire box
2019-06-21 15:47:42 -07:00
Eddie Hung
7acbea6b28
Fix alignment
2019-06-21 14:38:30 -07:00
Eddie Hung
f433a52374
Add FIXME about need for -mux4
2019-06-21 11:15:23 -07:00
Eddie Hung
c6b4653ebe
Since muxcover uses MUX4s, blast them back to gates here
2019-06-21 11:13:01 -07:00
Eddie Hung
dd22edcd28
Expand synth -coarse without wreduce, move muxcover
2019-06-21 11:12:32 -07:00
Eddie Hung
f11c9a419b
Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc
2019-06-20 17:38:16 -07:00
Eddie Hung
d1dadfcec8
Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc
2019-06-20 16:45:09 -07:00
Eddie Hung
9faab38e8d
mux_map to drop sign bit, and eliminate 'bx-es
2019-06-20 16:45:04 -07:00
Eddie Hung
4ca847a217
Merge remote-tracking branch 'origin/xaig' into xc7mux
2019-06-18 11:49:54 -07:00
Eddie Hung
8e0a47fb92
Really permute Xilinx LUT mappings as default LUT6.I5:A6
2019-06-18 11:48:48 -07:00
Eddie Hung
8f5e6d73ff
Revert "Fix (do not) permute LUT inputs, but permute mux selects"
...
This reverts commit da3d2eedd2
.
2019-06-18 11:35:21 -07:00