Eddie Hung
1d0ac659ad
Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too
2019-12-23 14:40:59 -08:00
Eddie Hung
75acaff6f5
Fix CEA/CEB check
2019-12-23 14:22:13 -08:00
Eddie Hung
edabe73377
Fix checking CE[AB] and for direct connections
2019-12-23 13:41:26 -08:00
Eddie Hung
71cac30309
Support unregistered cascades for A and B inputs
2019-12-23 12:38:18 -08:00
Eddie Hung
d00533eaa8
Add DSP48A* PCOUT -> PCIN cascade support
2019-12-23 11:42:46 -08:00
Eddie Hung
509070f82f
Disable clock domain partitioning in Yosys pass, let ABC do it
2019-12-23 08:36:20 -08:00
Marcin Kościelnicki
666c6128a9
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
Eddie Hung
1ea1e8e54f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-20 13:56:13 -08:00
Eddie Hung
1482f32d53
Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut
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Interpret "abc9 -lut" as lut string only if [0-9:]
2019-12-20 13:09:00 -08:00
Eddie Hung
979bf36fb0
Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t
2019-12-19 11:23:41 -08:00
Eddie Hung
94f15f023c
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-19 10:29:40 -08:00
Eddie Hung
269ba56a6d
Merge pull request #1581 from YosysHQ/clifford/fix1565
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Fix sim for assignments with lhs<rhs size
2019-12-19 12:24:27 -05:00
Eddie Hung
3b559de6e9
Interpret "abc9 -lut" as lut string only if [0-9:]
2019-12-18 12:21:12 -08:00
Eddie Hung
d0afe4e10d
Merge branch 'master' of github.com:YosysHQ/yosys
2019-12-18 12:08:38 -08:00
Eddie Hung
b2a42e1fac
Merge pull request #1572 from nakengelhardt/scratchpad_pass
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add a command to read/modify scratchpad contents
2019-12-18 13:55:44 -05:00
Marcin Kościelnicki
a235250403
xilinx: Add xilinx_dffopt pass ( #1557 )
2019-12-18 13:43:43 +01:00
N. Engelhardt
3671ecc7d0
use extra_args
2019-12-18 12:30:30 +01:00
Eddie Hung
c9c77a90b3
Remove &verify -s
2019-12-17 16:11:54 -08:00
Eddie Hung
b1b99e421e
Use pool<> instead of std::set<> to preserver ordering
2019-12-17 16:10:40 -08:00
Clifford Wolf
41ed6ca7a5
Fix sim for assignments with lhs<rhs size, fixes #1565
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-12-17 17:36:30 +01:00
Eddie Hung
dccd7eb39f
Cleanup
2019-12-17 00:25:08 -08:00
Eddie Hung
33e6d05585
Enforce non-existence
2019-12-16 17:06:30 -08:00
Eddie Hung
d9bf7061cd
Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flop
2019-12-16 16:49:48 -08:00
Eddie Hung
187e1c46e6
Update doc
2019-12-16 14:48:53 -08:00
Eddie Hung
4158ce4eda
More sloppiness, thanks @dh73 for spotting
2019-12-16 13:56:45 -08:00
Eddie Hung
6b384861e4
Oops
2019-12-16 13:31:05 -08:00
Eddie Hung
503d1db551
Implement 'attributes' grammar
2019-12-16 12:58:13 -08:00
Eddie Hung
952d62991f
Merge branch 'diego/memattr' of https://github.com/dh73/yosys into diego/memattr
2019-12-16 12:07:49 -08:00
Diego H
87e21b0122
Fixing compiler warning/issues. Moving test script to the correct place
2019-12-16 10:23:45 -06:00
N. Engelhardt
abcd82daca
add assert option to scratchpad command
2019-12-16 14:00:21 +01:00
Diego H
b35559fc33
Merging attribute rules into a single match block; Adding tests
2019-12-15 23:33:09 -06:00
Alyssa Milburn
e709fd3da1
Fix opt_expr.eqneq.cmpzero debug print
2019-12-15 20:40:38 +01:00
Diego H
266993408a
Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific
2019-12-13 15:43:24 -06:00
N. Engelhardt
ce3615b367
add periods and newlines to help message
2019-12-13 10:28:34 +01:00
Eddie Hung
bea15b537b
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-12 14:57:17 -08:00
N. Engelhardt
1187e91c2f
add test and make help message more verbose
2019-12-12 20:51:59 +01:00
N. Engelhardt
4c7cda1c8b
add a command to read/modify scratchpad contents
2019-12-12 16:25:03 +01:00
Eddie Hung
7e5602ad17
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr
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Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
2019-12-09 17:38:48 -08:00
Eddie Hung
36a88be609
ice40_wrapcarry -unwrap to preserve 'src' attribute
2019-12-09 14:28:54 -08:00
Eddie Hung
bbdf2452b3
-unwrap to create $lut not SB_LUT4 for opt_lut
2019-12-09 13:27:09 -08:00
Eddie Hung
500ed9b501
Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4
2019-12-09 12:45:22 -08:00
Eddie Hung
e05372778a
ice40_wrapcarry to really preserve attributes via -unwrap option
2019-12-09 11:48:28 -08:00
Eddie Hung
a46a7e8a67
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-06 23:22:52 -08:00
Eddie Hung
946d5854c0
Drop keep=0 attributes on SB_CARRY
2019-12-06 17:27:47 -08:00
Eddie Hung
ab667d3d47
Call abc9 with "&write -n", and parse_xaiger() to cope
2019-12-06 16:35:57 -08:00
Eddie Hung
fce527f4f7
Fix abc9 re-integration, remove abc9_control_wire, use cell->type as
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as part of clock domain for mergeability class
2019-12-06 16:20:18 -08:00
Eddie Hung
01a3cc29ba
abc9 to do clock partitioning again
2019-12-05 17:26:22 -08:00
Eddie Hung
02786b0aa0
Remove clkpart
2019-12-05 17:25:26 -08:00
Eddie Hung
a7e0cca480
Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER
2019-12-05 07:01:18 -08:00
Marcin Kościelnicki
2abe38e73e
iopadmap: Refactor and fix tristate buffer mapping. ( #1527 )
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The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
2019-12-04 08:44:08 +01:00
Eddie Hung
d66d06b91d
Add assertion
2019-12-03 19:21:42 -08:00
Eddie Hung
a181ff66d3
Add abc9_init wire, attach to abc9_flop cell
2019-12-03 18:47:09 -08:00
Eddie Hung
5897b918b3
ice40_wrapcarry to preserve SB_CARRY's attributes
2019-12-03 14:48:11 -08:00
Eddie Hung
6398b7c17c
Cleanup
2019-12-01 23:43:28 -08:00
Eddie Hung
1d87488795
Use pool instead of std::set for determinism
2019-12-01 23:26:17 -08:00
Eddie Hung
4ac1b92df3
Use pool<> not std::set<> for determinism
2019-12-01 23:19:32 -08:00
David Shah
e9ce4e658b
abc9: Fix breaking of SCCs
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Signed-off-by: David Shah <dave@ds0.me>
2019-12-01 20:44:56 +00:00
Eddie Hung
a26c52394f
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-28 12:58:30 -08:00
Eddie Hung
b3a66dff7c
Move \init signal for non-port signals as long as internally driven
2019-11-28 12:57:36 -08:00
Eddie Hung
130d3b9639
Fix multiple driver issue
2019-11-27 13:23:31 -08:00
Eddie Hung
ac5b5e97bc
Fix multiple driver issue
2019-11-27 13:21:59 -08:00
Eddie Hung
4bac6b13be
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-27 10:17:10 -08:00
Eddie Hung
cd2af66099
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-27 08:19:13 -08:00
Eddie Hung
1c0ee4f786
Do not replace constants with same wire
2019-11-27 08:18:41 -08:00
Eddie Hung
6464dc35ec
Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd
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xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder
2019-11-27 08:00:22 -08:00
Clifford Wolf
41e0ddf4f4
Merge pull request #1501 from YosysHQ/dave/mem_copy_attr
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memory_collect: Copy attr from RTLIL::Memory to cell
2019-11-27 11:25:23 +01:00
Eddie Hung
6338615aa1
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-27 01:02:16 -08:00
Eddie Hung
c7aa2c6b79
Cleanup
2019-11-27 01:01:24 -08:00
Eddie Hung
cb05fe0f70
Check for nullptr
2019-11-27 00:51:39 -08:00
Eddie Hung
d960feeeb0
Stray log_dump
2019-11-27 00:50:25 -08:00
Eddie Hung
8c813632b6
Revert "submod to bitty rather bussy, for bussy wires used as input and output"
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This reverts commit cba3073026
.
2019-11-27 00:48:22 -08:00
Eddie Hung
969f511415
Promote output wires in sigmap so that can be detected
2019-11-26 23:39:14 -08:00
Eddie Hung
5e487b103c
Fix submod -hidden
2019-11-26 23:26:25 -08:00
Eddie Hung
435d33c373
Add -hidden option to submod
2019-11-26 23:26:12 -08:00
Marcin Kościelnicki
fdcbda195b
opt_share: Fix handling of fine cells.
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Fixes #1525 .
2019-11-27 08:01:07 +01:00
Eddie Hung
2105ae176a
Check for either sign or zero extension for postAdd packing
2019-11-26 22:51:00 -08:00
Eddie Hung
09637dd3e4
Fix submod -hidden
2019-11-26 11:57:26 -08:00
Eddie Hung
3027f015c2
clkpart to use 'submod -hidden'
2019-11-26 11:35:32 -08:00
Eddie Hung
e8aa92ca35
Add -hidden option to submod
2019-11-26 11:35:15 -08:00
Eddie Hung
eb666b4677
Update docs with bullet points
2019-11-26 11:12:58 -08:00
Eddie Hung
0d7ba77426
Move \init from source wire to submod if output port
2019-11-25 16:07:47 -08:00
Eddie Hung
6831510f5b
Fix debug
2019-11-25 12:59:34 -08:00
Eddie Hung
d087024caf
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-25 12:42:09 -08:00
Eddie Hung
180cb39395
abc9 to contain time call
2019-11-25 12:35:57 -08:00
Eddie Hung
f50b6422b0
abc9 to no longer to clock partitioning, operate on whole modules only
2019-11-25 12:35:38 -08:00
Eddie Hung
63b7a48fbc
clkpart to analyse async flops too
2019-11-25 12:04:11 -08:00
Marcin Kościelnicki
6cdea425b8
clkbufmap: Add support for inverters in clock path.
2019-11-25 20:40:39 +01:00
Eddie Hung
23ecf12bbf
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-23 10:29:03 -08:00
Eddie Hung
15aa3f460d
More oopsies
2019-11-23 10:28:46 -08:00
Eddie Hung
bf1167bc64
Conditioning abc9 on POs not accurate due to cells
2019-11-23 10:26:55 -08:00
Eddie Hung
7b2bccb3d3
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-23 10:18:06 -08:00
Eddie Hung
722eeacc09
Print ".en=" only if there is an enable signal
2019-11-23 10:17:31 -08:00
Eddie Hung
907c8aeaef
Escape IdStrings
2019-11-23 10:16:56 -08:00
Eddie Hung
165f5cb6cf
More sane naming of submod
2019-11-23 10:01:09 -08:00
Eddie Hung
66ff0511a0
Add -set_attr option, -unpart to take attr name
2019-11-23 09:52:17 -08:00
Eddie Hung
fb49da21bd
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-23 08:39:19 -08:00
Eddie Hung
96941aacbb
Do not use log_signal() for empty SigSpec to prevent "{ }"
2019-11-22 23:29:10 -08:00
Eddie Hung
736b96b186
Call submod once, more meaningful submod names, ignore largest domain
2019-11-22 23:16:15 -08:00
Eddie Hung
1851f4b488
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-22 23:01:18 -08:00
Eddie Hung
d223e11a72
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 22:28:35 -08:00