This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
12,974
Commits
92
Branches
49
Tags
39
MiB
820232eaca
Commit Graph
1 Commits
Author
SHA1
Message
Date
Maciej Kurc
1f52332b8d
Added tests for Verilog frontent for attributes on parameters and localparams
...
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-05-16 12:53:43 +02:00