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479 Commits

Author SHA1 Message Date
Andrew Zonenberg e5109847c9 Fixed bug in GP_COUNTx model 2017-08-15 09:18:17 -07:00
Andrew Zonenberg 66b256d40e Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was high 2017-08-15 09:18:07 -07:00
Clifford Wolf 2cf0b5c157 Merge pull request #381 from azonenberg/countfix 
Added better behavioral models for GreenPAK counters. Refactored cells_sim into two files so analog/mixed signal stuff is separate
 2017-08-14 21:47:26 +02:00
Robert Ou 78fd24f40f coolrunner2: Add INVERT parameter to some BUFGs 2017-08-14 12:13:33 -07:00
Robert Ou 1e3ffd57cb coolrunner2: Add FFs with clock enable to cells_sim.v 2017-08-14 12:13:25 -07:00
Andrew Zonenberg 348acbd968 Fixed typo in GP_COUNT8 sim model 2017-08-14 10:45:40 -07:00
Andrew Zonenberg c205d571df Fixed typo in error message 2017-08-14 10:45:40 -07:00
Andrew Zonenberg 0a6c702c41 Changed LEVEL resets for GP_COUNTx to be properly synthesizeable 2017-08-14 10:45:40 -07:00
Andrew Zonenberg 9f3dc59ffe Changed LEVEL resets to be edge triggered anyway 2017-08-14 10:45:40 -07:00
Andrew Zonenberg b049ead042 Added level-triggered reset support to GP_COUNTx simulation models 2017-08-14 10:45:40 -07:00
Andrew Zonenberg ac75524f69 Fixed undeclared "count" in GP_COUNT8_ADV 2017-08-14 10:45:39 -07:00
Andrew Zonenberg db20e3f1c2 Fixed undeclared "count" in GP_COUNT14_ADV 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 3618ca2218 Fixed typo in last commit 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 4da1a327c0 Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock divide, but do everything else. 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 4504dd78e9 Fixed typo in COUNT8 model 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 60dd5dba7b Moved GP_POR out of digital cells b/c it has delays 2017-08-14 10:45:39 -07:00
Andrew Zonenberg f55d4cc2fd Improved cells_sim_digital model for GP_COUNT8 2017-08-14 10:45:39 -07:00
Andrew Zonenberg fe3a932cfa Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital 2017-08-14 10:45:39 -07:00
Clifford Wolf 8a69759306 Add techlibs/xilinx/lut2lut.v 2017-07-10 12:09:05 +02:00
Clifford Wolf 621787a9e0 Fix some c++ clang compiler errors 2017-07-03 19:38:30 +02:00
Clifford Wolf 5c1c126374 Apply minor coding style changes to coolrunner2 target 2017-07-03 19:35:40 +02:00
Clifford Wolf 6afee022ad Merge pull request #352 from rqou/master 
Initial Coolrunner-II support
 2017-07-03 19:33:36 +02:00
Robert Ou b102c0e254 coolrunner2: Add a few more primitives 
These cannot be inferred yet, but add them to cells_sim.v for now
 2017-06-25 23:58:28 -07:00
Robert Ou 36b75dfcb7 coolrunner2: Initial mapping of latches 2017-06-25 23:58:28 -07:00
Robert Ou 4af5baab21 coolrunner2: Initial mapping of DFFs 
All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N
(negative-edge triggered)
 2017-06-25 23:58:28 -07:00
Robert Ou 1eb5dee799 coolrunner2: Remove redundant INVERT_PTC 2017-06-25 23:58:28 -07:00
Robert Ou ffff001008 coolrunner2: Remove debug prints 2017-06-25 23:58:28 -07:00
Robert Ou 5798105d47 coolrunner2: Correctly handle $_NOT_ after $sop 2017-06-25 23:58:28 -07:00
Robert Ou 908ce3fdce coolrunner2: Also construct the XOR cell in the macrocell 2017-06-25 23:58:28 -07:00
Robert Ou a64b56648d coolrunner2: Initial techmapping for $sop 2017-06-25 23:58:22 -07:00
Andrew Zonenberg cbdddc3af9 greenpak4_counters: Changed generation of primitive names so that the absorbed register's name is included 2017-06-24 14:54:07 -07:00
Robert Ou 6e0fb889fa coolrunner2: Initial commit 2017-06-24 07:22:56 -07:00
Clifford Wolf e7a984a4df Add dff2ff.v techmap file 2017-05-31 11:45:58 +02:00
Andrew Zonenberg 184bd148c9 greenpak4_counters: Added support for parallel output from GP_COUNTx cells 2017-05-22 19:39:55 -07:00
Clifford Wolf 05cdd58c8d Add $_ANDNOT_ and $_ORNOT_ gates 2017-05-17 09:08:29 +02:00
Larry Doolittle 2021ddecb3 Squelch trailing whitespace 2017-04-12 15:11:09 +02:00
dh73 c27dcc1e47 Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs 2017-04-05 23:01:29 -05:00
Clifford Wolf f3324ed0cc Merge branch 'master' of github.com:cliffordwolf/yosys 2017-02-25 13:08:27 +01:00
Clifford Wolf 5f1d0b1024 Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00
Andrew Zonenberg 6fed2dc996 Merge https://github.com/cliffordwolf/yosys 2017-02-14 08:29:37 -08:00
Clifford Wolf 2a311c2c38 Fix double-call of log_pop() in synth_greenpak4 2017-02-14 11:57:54 +01:00
Andrew Zonenberg 0d7e71f7ab Merge https://github.com/cliffordwolf/yosys 2017-02-08 22:12:29 -08:00
Clifford Wolf 3928482a3c Add $cover cell type and SVA cover() support 2017-02-04 14:14:26 +01:00
Andrew Zonenberg 27a626ce98 greenpak4: Added POUT to GP_COUNTx cells 2017-01-01 00:56:20 -08:00
Andrew Zonenberg ada98844b9 greenpak4: Added INT pin to GP_SPI 2016-12-21 11:35:29 +08:00
Andrew Zonenberg 6b526e9382 greenpak4: removed unused MISO pin from GP_SPI 2016-12-21 11:33:32 +08:00
Andrew Zonenberg 638f3e3b12 greenpak4: Removed SPI_BUFFER parameter 2016-12-20 13:07:49 +08:00
Andrew Zonenberg 073e8df9f1 greenpak4: replaced MOSI/MISO with single one-way SDAT pin 2016-12-20 12:34:56 +08:00
Andrew Zonenberg d4a05b499e greenpak4: Changed port names on GP_SPI for clarity 2016-12-20 10:30:38 +08:00
Andrew Zonenberg eb80ec84aa greenpak4: Initial implementation of GP_SPI cell 2016-12-20 09:58:02 +08:00
Andrew Zonenberg de1d81511a greenpak4: Updated GP_DCMP cell model 2016-12-17 12:01:22 +08:00
Andrew Zonenberg 7cdba8432c greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF. 2016-12-16 15:14:20 +08:00
Andrew Zonenberg bea6e2f11f greenpak4: Initial version of GP_DCMP skeleton (not yet usable). Changed interface to GP_DCMPMUX 2016-12-15 15:19:35 +08:00
Andrew Zonenberg 3690aa556c greenpak4: More fixups of GP_DCMPx cells 2016-12-15 07:19:08 +08:00
Andrew Zonenberg 3491d33863 greenpak4: And another typo :( 2016-12-15 07:17:07 +08:00
Andrew Zonenberg ea787e6be3 greenpak4: Fixed another typo 2016-12-15 07:16:26 +08:00
Andrew Zonenberg 58da621ac3 greenpak4: Fixed typo 2016-12-15 07:15:38 +08:00
Andrew Zonenberg 262f8f913c greenpak4: Cleaned up trailing spaces in cells_sim 2016-12-14 14:14:45 +08:00
Andrew Zonenberg c77e6e6114 greenpak4: Added GP_DCMPREF / GP_DCMPMUX 2016-12-14 14:14:26 +08:00
Andrew Zonenberg c3c2983d12 Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUF 2016-12-11 10:04:00 +08:00
Andrew Zonenberg 8f3d1f8fcf greenpak4: Added support for inferred input/output inverters on latches 2016-12-10 19:58:32 +08:00
Andrew Zonenberg c53a33143e greenpak4: Can now techmap inferred D latches (without set/reset or output inverter) 2016-12-10 18:46:36 +08:00
Andrew Zonenberg 797c03997e greenpak4: Inverted D latch cells now have nQ instead of Q as output port name for consistency 2016-12-10 13:57:37 +08:00
Andrew Zonenberg 8767cdcac9 Added GP_DLATCH and GP_DLATCHI 2016-12-05 23:49:06 -08:00
Andrew Zonenberg 981f014301 Initial implementation of techlib support for GreenPAK latches. Instantiation only, no behavioral inference yet. 2016-12-05 21:22:41 -08:00
Andrew Zonenberg e6ab00d419 Updated help text for synth_greenpak4 2016-12-05 20:11:37 -08:00
Clifford Wolf e9d73d2ee0 Indenting fixes in gowin sim cell lib 2016-11-08 18:54:00 +01:00
Clifford Wolf 3db2ac4e00 Added hex constant support to write_verilog 2016-11-03 12:13:23 +01:00
Clifford Wolf 81bdf0ad0f iCE40 flow is not experimental anymore 2016-11-01 11:32:02 +01:00
Clifford Wolf cae5131bac Added initial version of "synth_gowin" 2016-11-01 11:31:13 +01:00
Andrew Zonenberg 1cca1563c6 Fixed typo in last commit 2016-10-18 20:46:49 -07:00
Andrew Zonenberg e78fa157a3 greenpak4: Added GP_PGEN cell definition 2016-10-18 20:42:44 -07:00
Andrew Zonenberg 091d32b563 Added GLITCH_FILTER parameter to GP_DELAY 2016-10-18 19:53:19 -07:00
Andrew Zonenberg a818472f0c greenpak4: added model for GP_EDGEDET block 2016-10-18 19:33:26 -07:00
Andrew Zonenberg d6feb4b43e greenpak4: Changed parameters for GP_SYSRESET 2016-10-16 22:53:43 -07:00
Clifford Wolf bdc316db50 Added $anyseq cell type 2016-10-14 15:24:03 +02:00
Clifford Wolf 53655d173b Added $global_clock verilog syntax support for creating $ff cells 2016-10-14 12:33:56 +02:00
Clifford Wolf 8ebba8a35f Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00
Clifford Wolf 76352c99c9 Added "prep -nokeepdc" 2016-09-30 17:02:52 +02:00
Clifford Wolf 2ee9bf10d0 Added "prep -nomem" 2016-08-30 23:57:24 +02:00
Clifford Wolf 6f41e5277d Removed $aconst cell type 2016-08-30 19:09:56 +02:00
Clifford Wolf eae390ae17 Removed $predict again 2016-08-28 21:35:33 +02:00
Clifford Wolf d77a914683 Added "wreduce -memx" 2016-08-20 12:52:50 +02:00
Clifford Wolf 15ef608453 Added memory_memx pass, "memory -memx", and "prep -memx" 2016-08-19 19:48:26 +02:00
Clifford Wolf 5d90a5b905 Added greenpak4_dffinv 2016-08-15 09:33:06 +02:00
Andrew Zonenberg 0b0ba96488 greenpak4: Changed name of inverted output ports for consistency 2016-08-14 00:30:45 -07:00
Andrew Zonenberg 3b9756c6a3 greenpak4: Added GP_DFFxI cells 2016-08-14 00:11:44 -07:00
Andrew Zonenberg 2b062c48cb greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6) 2016-08-13 22:27:58 -07:00
whitequark 0515809448 synth_greenpak4: use attrmvcp to move LOC from wires to cells. 2016-08-10 20:09:35 +00:00
Clifford Wolf 4056312987 Added $anyconst and $aconst 2016-07-27 15:41:22 +02:00
Clifford Wolf 5c166e76e5 Added $initstate cell type and vlog function 2016-07-21 14:23:22 +02:00
Clifford Wolf d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf 721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Andrew Zonenberg 52a738a544 Added GP_DAC cell 2016-07-11 22:45:55 -07:00
Andrew Zonenberg baae472b83 Removed VOUT port of GP_BANDGAP 2016-07-11 22:45:42 -07:00
Andrew Zonenberg 8619d33114 Removed splitnets in prep for new gp4par parser 2016-07-11 22:42:25 -07:00
Clifford Wolf cdb58f68ab Added "prep -auto-top" and "synth -auto-top" 2016-07-11 11:40:55 +02:00
whitequark c0645839fe greenpak4: add GP_COUNT{8,14}_ADV cells. 2016-07-10 15:46:46 +00:00
Clifford Wolf 21659847a7 Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations 2016-07-08 14:41:36 +02:00
Clifford Wolf df5ebfa0a0 Improved ice40_ffinit error reporting 2016-06-30 09:58:13 +02:00