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yosys
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2026 Commits

Author SHA1 Message Date
Clifford Wolf 816fe6bbe0 Added Xilinx example for Basys3 board 2015-02-01 17:09:34 +01:00
Clifford Wolf 6978f3a77b Added EDIF backend support for multi-bit cell ports 2015-02-01 15:43:35 +01:00
Clifford Wolf 1b159bc955 Added missing ports and parameters to xilinx brams 2015-02-01 15:42:59 +01:00
Clifford Wolf 1df81f92ce Added "make mklibyosys", some minor API changes 2015-02-01 13:38:46 +01:00
Clifford Wolf 3fe2441185 Minor README changes 2015-02-01 00:57:12 +01:00
Clifford Wolf b59bb8a528 Removed TODO list from README file 2015-02-01 00:48:22 +01:00
Clifford Wolf 9948ff2d8a Added yosys_banner(), Updated Copyright range 2015-02-01 00:39:59 +01:00
Clifford Wolf 07326943e7 Added <algorithm> include to hashlib.h 2015-02-01 00:27:07 +01:00
Clifford Wolf 9abbeefe6e Using selections in "ls" command 2015-02-01 00:13:19 +01:00
Clifford Wolf fb8c755726 Shorter "dump" options 2015-01-31 23:52:36 +01:00
Clifford Wolf 8dfa105255 Bugfix in opt_const $eq -> buffer code 2015-01-31 23:25:32 +01:00
Clifford Wolf 67218443be Log msg change 2015-01-31 21:26:53 +01:00
Clifford Wolf 1d92915a55 Fixed equiv_make for partially undriven nets (e.g. after "clean -purge") 2015-01-31 21:07:42 +01:00
Clifford Wolf bc86b4a7e9 Added "equiv_induct -undef" 2015-01-31 13:58:04 +01:00
Clifford Wolf e9cfc4a453 Added "equiv_simple -undef" 2015-01-31 13:06:41 +01:00
Clifford Wolf f80f5b721d Added "equiv_make -blacklist <file> -encfile <file>" 2015-01-31 12:08:20 +01:00
Clifford Wolf cb9d0a414d Synced RTLIL::unescape_id() to log_id() behavior 2015-01-30 22:51:16 +01:00
Clifford Wolf bedd46338f Added "fsm -encfile" 2015-01-30 22:46:53 +01:00
Clifford Wolf aabd5097ed More log_id() stuff 2015-01-30 22:22:52 +01:00
Clifford Wolf 114a78d11a Some cleanups in log.cc 2015-01-30 22:12:26 +01:00
Clifford Wolf 9ebf803cbe Improved an error message 2015-01-28 00:46:00 +01:00
Clifford Wolf df64542288 Fixed bug in equiv_miter 2015-01-28 00:34:30 +01:00
Clifford Wolf 23e54bda81 Added "sat -show-ports" 2015-01-27 23:04:28 +00:00
Clifford Wolf e666611534 Bugfix in resource sharing test 2015-01-27 19:30:06 +01:00
Clifford Wolf c7c99a694b Updaed ABC to hg rev 61ad5f908c03 2015-01-27 19:22:56 +01:00
Clifford Wolf 13b50bacfe Rethrow with "catch(...) throw;" 2015-01-25 22:57:09 +01:00
Clifford Wolf acfaeb8d34 Added equiv_remove 2015-01-25 14:20:22 +01:00
Clifford Wolf 66a6b86daa Added equiv_miter 2015-01-25 14:00:49 +01:00
Clifford Wolf 2a9ad48eb6 Added ENABLE_NDEBUG makefile options 2015-01-24 12:16:46 +01:00
Clifford Wolf 8fe9ab50e5 Added #ifdef NDEBUG for log_assert() 2015-01-24 11:49:34 +01:00
Clifford Wolf 909a95182b Fixed xilinx FDSE sim model 2015-01-24 11:03:22 +01:00
Clifford Wolf 75bbeb828a Various equiv_* improvements 2015-01-24 00:32:24 +01:00
Clifford Wolf 43951099cf Added dict/pool.sort() 2015-01-24 00:13:27 +01:00
Clifford Wolf 1cb4c925d0 Improvements in equiv_make, equiv_induct 2015-01-22 21:23:01 +01:00
Clifford Wolf 5707ba22c1 Improved xdot calling 2015-01-22 20:45:53 +01:00
Clifford Wolf f6d94e8720 Added equiv_induct 2015-01-22 14:03:18 +01:00
Clifford Wolf a6aa32e762 Various equiv_simple improvements 2015-01-22 13:42:04 +01:00
Clifford Wolf 0a225f8b27 Moved equiv stuff to passes/equiv/ 2015-01-22 12:03:15 +01:00
Clifford Wolf abf8398216 Progress in equiv_simple 2015-01-21 23:59:58 +00:00
Clifford Wolf 74e1de1fac Fixed opt_muxtree performance bug 2015-01-21 16:44:07 +01:00
Clifford Wolf 0bfec8e24c Faster "make clean-abc" 2015-01-20 23:17:53 +00:00
Clifford Wolf 81020269b2 README stuff 2015-01-20 20:59:50 +00:00
Clifford Wolf 5febbe3620 Added equiv_simple 2015-01-19 15:08:44 +01:00
Clifford Wolf 615c2e136e Added equiv_status 2015-01-19 14:20:04 +01:00
Clifford Wolf 76c5d863c5 Added equiv_make command 2015-01-19 13:59:08 +01:00
Clifford Wolf e13a45ae61 Added $equiv cell type 2015-01-19 11:55:05 +01:00
Clifford Wolf 3a58b8d5b5 Merge branch 'master' of github.com:cliffordwolf/yosys 2015-01-18 19:47:06 +01:00
Clifford Wolf d29d26f882 Various cleanups in xilinx techlib 2015-01-18 19:43:54 +01:00
Clifford Wolf 8d295730e5 Refactoring of memory_bram and xilinx brams 2015-01-18 19:05:29 +01:00
Clifford Wolf f6f51cd68a Merge pull request #47 from mschmoelzer/master 
Add "echo-yosys-ver" and "echo-git-rev" Makefile targets.
 2015-01-18 16:39:55 +01:00