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77 Commits

Author SHA1 Message Date
Udi Finkelstein 2b9c75f8e3 This PR should be the base for discussion, do not merge it yet! 
It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.

What it DOES'T do:
Detect registers connected to output ports of instances.

Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.

You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
 2018-03-11 23:09:34 +02:00
Clifford Wolf c80315cea4 Bugfix in hierarchy handling of blackbox module ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-05 13:28:45 +01:00
Udi Finkelstein eb40278a16 Turned a few member functions into const, esp. dumpAst(), dumpVlog(). 2017-09-30 07:37:38 +03:00
Clifford Wolf 5f1d0b1024 Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00
Clifford Wolf 3928482a3c Add $cover cell type and SVA cover() support 2017-02-04 14:14:26 +01:00
Clifford Wolf 97583ab729 Avoid creation of bogus initial blocks for assert/assume in always @* 2016-09-06 17:34:42 +02:00
Clifford Wolf eae390ae17 Removed $predict again 2016-08-28 21:35:33 +02:00
Clifford Wolf 82a4a0230f Another bugfix in mem2reg code 2016-08-21 13:23:58 +02:00
Clifford Wolf a7b0769623 Added "read_verilog -dump_rtlil" 2016-07-27 15:40:17 +02:00
Clifford Wolf d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf 721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Ruben Undheim 178ff3e7f6 Added support for SystemVerilog packages with localparam definitions 2016-06-18 10:53:55 +02:00
Clifford Wolf ee071586c5 Fixed access-after-delete bug in mem2reg code 2016-05-27 17:25:33 +02:00
Clifford Wolf 5a09fa4553 Fixed handling of parameters and const functions in casex/casez pattern 2016-04-21 15:31:54 +02:00
Clifford Wolf 84bf862f7c Spell check (by Larry Doolittle) 2015-08-14 10:56:05 +02:00
Clifford Wolf 8d6d5c30d9 Added WORDS parameter to $meminit 2015-07-31 10:40:09 +02:00
Clifford Wolf 4513ff1b85 Fixed nested mem2reg 2015-07-29 16:37:08 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf 1f1deda888 Added non-std verilog assume() statement 2015-02-26 18:47:39 +01:00
Clifford Wolf 7f1a1759d7 Added "read_verilog -nomeminit" and "nomeminit" attribute 2015-02-14 11:21:12 +01:00
Clifford Wolf a8e9d37c14 Creating $meminit cells in verilog front-end 2015-02-14 10:49:30 +01:00
Clifford Wolf 90bc71dd90 dict/pool changes in ast 2014-12-29 03:11:50 +01:00
Clifford Wolf 137f35373f Changed more code to dict<> and pool<> 2014-12-28 19:24:24 +01:00
Clifford Wolf a6c96b986b Added Yosys::{dict,nodict,vector} container types 2014-12-26 10:53:21 +01:00
Clifford Wolf 70b2efdb05 Added support for $readmemh/$readmemb 2014-10-26 20:33:10 +01:00
Clifford Wolf 6b05a9e807 Fixed handling of invalid array access in mem2reg code 2014-10-16 00:44:23 +02:00
Clifford Wolf 085c8e873d Added AstNode::asInt() 2014-08-21 17:11:51 +02:00
Clifford Wolf 7bfc4ae120 Added Verilog/AST support for DPI functions (dpi_call() still unimplemented) 2014-08-21 12:43:51 +02:00
Clifford Wolf acb435b6cf Added const folding of AST_CASE to AST simplifier 2014-08-18 00:02:30 +02:00
Clifford Wolf d491fd8c19 Use stackmap<> in AST ProcessGenerator 2014-08-17 00:57:24 +02:00
Clifford Wolf c83b990458 Changed the AST genWidthRTLIL subst interface to use a std::map 2014-08-14 23:02:07 +02:00
Clifford Wolf d259abbda2 Added AST_MULTIRANGE (arrays with more than 1 dimension) 2014-08-06 15:52:54 +02:00
Clifford Wolf 91dd87e60b Improved scope resolution of local regs in Verilog+AST frontend 2014-08-05 12:15:53 +02:00
Clifford Wolf 1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf 27a872d1e7 Added support for "upto" wires to Verilog front- and back-end 2014-07-28 14:25:03 +02:00
Clifford Wolf 80e4594695 Added AstNode::MEM2REG_FL_CMPLX_LHS 2014-06-17 21:39:25 +02:00
Clifford Wolf 5bfe865cec Added found_real feature to AstNode::detectSignWidth 2014-06-16 15:00:57 +02:00
Clifford Wolf 149fe83a8d improved (fixed) conversion of real values to bit vectors 2014-06-14 21:00:51 +02:00
Clifford Wolf 442a8e2875 Implemented basic real arithmetic 2014-06-14 08:51:22 +02:00
Clifford Wolf 7ef0da32cd Added Verilog lexer and parser support for real values 2014-06-13 11:29:23 +02:00
Clifford Wolf e275e8eef9 Add support for cell arrays 2014-06-07 11:48:50 +02:00
Clifford Wolf 7c8a7b2131 further improved const function support 2014-06-07 00:02:05 +02:00
Clifford Wolf 76da2fe172 improved const function support 2014-06-06 22:55:02 +02:00
Clifford Wolf b5cd7a0179 added while and repeat support to verilog parser 2014-06-06 17:40:04 +02:00
Clifford Wolf 02e6f2c5be Added Verilog support for "`default_nettype none" 2014-02-17 14:28:52 +01:00
Clifford Wolf e8af3def7f Added support for FOR loops in function calls in parameters 2014-02-14 20:33:22 +01:00
Clifford Wolf 534c1a5dd0 Created basic support for function calls in parameter values 2014-02-14 19:56:44 +01:00
Clifford Wolf cd9e8741a7 Implemented read_verilog -defer 2014-02-13 13:59:13 +01:00
Clifford Wolf d06258f74f Added constant size expression support of sized constants 2014-02-01 13:50:23 +01:00
Clifford Wolf 375c4dddc1 Added read_verilog -icells option 2014-01-29 00:59:28 +01:00