Commit Graph

163 Commits

Author SHA1 Message Date
Claire Xen 55e8f5061a
Merge pull request #2817 from YosysHQ/claire/fixemails
Fixing old e-mail addresses and deadnames
2021-06-09 13:22:52 +02:00
Claire Xenia Wolf a734face3a More deadname stuff 2021-06-09 12:33:41 +02:00
Zachary Snow 2e697f5655 verilog: check for module scope identifiers during width detection
The recent fix for case expression width detection causes the width of
the expressions to be queried before they are simplified. Because the
logic supporting module scope identifiers only existed in simplify,
looking them up would fail during width detection. This moves the logic
to a common helper used in both simplify() and detectSignWidthWorker().
2021-06-08 15:03:16 -04:00
Zachary Snow c79fbfe0a1 mem2reg: tolerate out of bounds constant accesses
This brings the mem2reg behavior in line with the nomem2reg behavior.
2021-06-08 15:02:57 -04:00
Zachary Snow 0795b3ec07 verilog: fix case expression sign and width handling
- The case expression and case item expressions are extended to the
  maximum width among them, and are only interpreted as signed if all of
  them are signed
- Add overall width and sign detection for AST_CASE
- Add sign argument to genWidthRTLIL helper
- Coverage for both const and non-const case statements
2021-05-25 16:16:46 -04:00
Zachary Snow 15f35d6754 sv: support remaining assignment operators
- Add support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
- Unify existing support for: +=, -=, &=, |=, ^=
2021-05-25 16:15:57 -04:00
Xiretza 092e923330 verilog: fix buf/not primitives with multiple outputs
From IEEE1364-2005, section 7.3 buf and not gates:

> These two logic gates shall have one input and one or more outputs.
> The last terminal in the terminal list shall connect to the input of the
> logic gate, and the other terminals shall connect to the outputs of
> the logic gate.

yosys does not follow this and instead interprets the first argument as
the output, the second as the input and ignores the rest.
2021-03-17 11:44:03 -04:00
Zachary Snow 4f187d53c5 verilog: support module scope identifiers in parametric modules 2021-03-16 11:01:30 -04:00
Zachary Snow 1ec5994100 verilog: fix handling of nested ifdef directives
- track depth so we know whether to consider higher-level elsifs
- error on unmatched endif/elsif/else
2021-03-01 12:28:33 -05:00
whitequark 326f1c9db4
Merge pull request #2573 from zachjs/repeat-call
verilog: refactored constant function evaluation
2021-02-11 19:56:41 +00:00
Zachary Snow 1d5f3fe506 verlog: allow shadowing module ports within generate blocks
This is a somewhat obscure edge case I encountered while working on test
cases for earlier changes. Declarations in generate blocks should not be
checked against the list of ports. This change also adds a check
forbidding declarations within generate blocks being tagged as inputs or
outputs.
2021-02-07 11:48:39 -05:00
Zachary Snow b93b6f4285 verilog: refactored constant function evaluation
Elaboration now attempts constant evaluation of any function call with
only constant arguments, regardless of the context or contents of the
function. This removes the concept of "recommended constant evaluation"
which previously applied to functions with `for` loops or which were
(sometimes erroneously) identified as recursive. Any function call in a
constant context (e.g., `localparam`) or which contains a constant-only
procedural construct (`while` or `repeat`) in its body will fail as
before if constant evaluation does not succeed.
2021-02-04 10:18:27 -05:00
whitequark baf1875307
Merge pull request #2529 from zachjs/unnamed-genblk
verilog: significant block scoping improvements
2021-02-04 09:57:28 +00:00
whitequark 4bc6995b9a
Merge pull request #2436 from dalance/fix_generate
Fix begin/end in generate
2021-02-03 09:43:23 +00:00
Zachary Snow fe74b0cd95 verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.

Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.

1. Unlabled generate blocks are now implicitly named according to the LRM in
   `label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
   synthetic unnamed generate block to avoid creating extra hierarchy levels
   where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
   of the topmost scope, which is necessary because such wires and cells often
   appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
   invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
   scope, completely deferring the inspection and elaboration of nested scopes;
   names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
   to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
   in largely the same manner as other blocks
     before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
      after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
   than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
   prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
   or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode

Addresses the following issues: 656, 2423, 2493
2021-01-31 09:42:09 -05:00
Zachary Snow 27257a419f verilog: strip leading and trailing spaces in macro args 2021-01-28 11:26:35 -05:00
Zachary Snow 4fadcc8f25 verilog: allow spaces in macro arguments 2021-01-20 08:49:58 -07:00
dalance 84ecb321b4 Fix begin/end in generate 2020-11-11 12:03:37 +09:00
Xiretza e38b830cbb
tests/simple: remove "nullglob" shopt 2020-09-21 15:07:02 +02:00
Zachary Snow 6127f22788 Module name scope support 2020-08-20 20:15:08 -04:00
clairexen 22765ef0a5
Merge pull request #2339 from zachjs/display-format-0s
Allow %0s $display format specifier
2020-08-18 17:39:01 +02:00
clairexen 4aa0dc4dc7
Merge pull request #2338 from zachjs/const-branch-finish
Propagate const_fold through generate blocks and branches
2020-08-18 17:38:07 +02:00
Zachary Snow 2ee0b8ebea Propagate const_fold through generate blocks and branches 2020-08-09 17:21:08 -04:00
Zachary Snow 96ec9acf84 Allow %0s $display format specifier 2020-08-09 17:19:49 -04:00
Zachary Snow c3e95eb1ab Fix generate scoping issues
- expand_genblock defers prefixing of items within named sub-blocks
- Allow partially-qualified references to local scopes
- Handle shadowing within generate blocks
- Resolve generate scope references within tasks and functions
- Apply generate scoping to genvars
- Resolves #2214, resolves #1456
2020-07-31 20:32:47 -06:00
Xiretza 6a2bac21d3
Expand tests/simple/constmuldivmod.v 2020-05-28 22:59:04 +02:00
Claire Wolf f38d76efbf Bugfix in partsel.v signed indices test cases
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
Claire Wolf 749c2ff84a Add tests based on the test case from #1990
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
Eddie Hung 3df66027e0 Add dynamic slicing Verilog testcase 2020-03-31 11:51:31 -07:00
Claire Wolf a7cc4673c3 Fix partsel expr bit width handling and add test case
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-08 16:12:12 +01:00
Eddie Hung 23fcfd0adb Make SV2017 compliant courtesy of @wsnyder 2019-12-12 07:34:07 -08:00
Eddie Hung ef0681ea4c simple/peepopt.v tests to various/peepopt.ys with equiv_opt & select 2019-09-05 08:43:22 -07:00
Eddie Hung 0cee66e759 Add peepopt_dffmuxext tests 2019-09-04 12:34:44 -07:00
Emily 69a5dea89e Use `command -v` rather than `which` 2019-09-03 00:57:32 +01:00
Clifford Wolf 6ffb910d12 Add test case for real parameters
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-20 11:38:21 +02:00
Jim Lawson 3b8c917025 Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
Use FIRRTL spec vlaues for definition of FIRRTL widths.
Added support for '$pos`, `$pow` and `$xnor` cells.
Enable tests/simple/operators.v since all operators tested there are now supported.
Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
2019-07-31 09:27:38 -07:00
Eddie Hung c20adc5263 Add test 2019-06-20 16:07:22 -07:00
Clifford Wolf 6a6dd5e057 Add proper test for SV-style arrays
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 12:06:07 +02:00
Clifford Wolf fa5fc3f6af Add defvalue test, minor autotest fixes for .sv files
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 12:12:08 +02:00
Clifford Wolf f01a61f093 Rename implicit_ports.sv test to implicit_ports.v
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-07 13:12:25 +02:00
Clifford Wolf a0b57f2a6f Cleanup tux3-implicit_named_connection
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-07 11:46:16 +02:00
Clifford Wolf b637b3109d Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3-implicit_named_connection 2019-06-07 11:41:54 +02:00
tux3 88f5977093 SystemVerilog support for implicit named port connections
This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
2019-06-06 18:07:49 +02:00
Maciej Kurc 5739cf5265 Added tests for attributes
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-06-03 09:25:20 +02:00
Clifford Wolf 349c47250a
Merge pull request #1049 from YosysHQ/clifford/fix1047
Do not use shiftmul peepopt pattern when mul result is truncated
2019-05-28 19:02:26 +02:00
Clifford Wolf cb285e4b87 Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-28 17:17:56 +02:00
Clifford Wolf e3ebac44df Add actual wandwor test that is part of "make test"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-28 16:42:50 +02:00
Maciej Kurc 1f52332b8d Added tests for Verilog frontent for attributes on parameters and localparams
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-05-16 12:53:43 +02:00
Clifford Wolf b7ec698d40 Add test case from #997
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-07 19:58:04 +02:00
Clifford Wolf d187be39d6 Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968 2019-05-06 15:41:13 +02:00