7 Commits

Author	SHA1	Message	Date
Marcelina Kościelnicka	89c74ffd71	verilog: Use proc memory writes in the frontend.	2021-03-08 20:16:29 +01:00
Rodrigo Alejandro Melo	e9dc2759c4	Fixed some missing "verilog_" in documentation	2019-12-13 10:17:05 -03:00
Clifford Wolf	84bf862f7c	Spell check (by Larry Doolittle)	2015-08-14 10:56:05 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
Ruben Undheim	79cbf9067c	Corrected spelling mistakes found by lintian	2014-09-06 08:47:06 +02:00
Clifford Wolf	36c39cbd04	Added RTLIL and Liberty syntax highlighting to manual	2013-07-25 14:00:16 +02:00
Clifford Wolf	61ed6b32d1	Added Yosys Manual	2013-07-20 15:19:12 +02:00