Clifford Wolf
706631225e
Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types
2015-04-05 09:45:14 +02:00
Clifford Wolf
c52a4cdeed
Added "dffinit", Support for initialized Xilinx DFF
2015-04-04 19:00:15 +02:00
Clifford Wolf
4b44907619
documentation improvements
2015-03-29 20:22:08 +02:00
Clifford Wolf
68bbb15214
Fixed detection of absolute paths in ABC for win32
2015-03-22 11:03:56 +01:00
Clifford Wolf
8b1e0bdd9e
Fixed handling of quotes in liberty parser
2015-03-18 16:03:19 +01:00
Clifford Wolf
aed4d763cf
Added hierarchy -auto-top
2015-03-18 08:33:40 +01:00
Clifford Wolf
ed15400fc6
Fixed bug in "hierarchy" for parametric designs
2015-03-04 15:52:34 +01:00
Clifford Wolf
1f1deda888
Added non-std verilog assume() statement
2015-02-26 18:47:39 +01:00
Clifford Wolf
27a918eadf
Merge branch 'master' of github.com:cliffordwolf/yosys
2015-02-25 23:01:54 +01:00
Clifford Wolf
331f8b8d0b
Bugfix in iopadmap
2015-02-25 23:01:42 +01:00
Clifford Wolf
3fe18c26cd
Added "keep_hierarchy" attribute
2015-02-25 12:46:00 +01:00
Clifford Wolf
9ae21263f0
Some cleanups in "clean"
2015-02-24 22:31:30 +01:00
Clifford Wolf
81fa4e81a6
Fixed compilation problems with gcc 4.6.3; use enum instead of const ints.
...
(original patch by Andrew Becker <andrew.becker@epfl.ch>)
2015-02-24 11:01:00 +01:00
Clifford Wolf
c4f383e452
Fixed "check -assert"
2015-02-22 16:29:44 +01:00
Clifford Wolf
d361d313e1
Added "check -assert" doc
2015-02-22 13:02:48 +01:00
Clifford Wolf
e8307cefd9
Added "check -assert"
2015-02-22 13:00:41 +01:00
Clifford Wolf
39d25b212c
Fixed "sat -initsteps" off-by-one bug
2015-02-22 12:42:05 +01:00
Clifford Wolf
fae0e75ace
Added "sat -stepsize" and "sat -tempinduct-step"
2015-02-21 22:52:49 +01:00
Clifford Wolf
b19c926af8
sat docu change
2015-02-21 22:03:54 +01:00
Clifford Wolf
9237fb924e
When "sat -tempinduct-baseonly -maxsteps N" reaches maxsteps it is a good thing.
2015-02-21 20:05:16 +01:00
Clifford Wolf
1688b9b464
Added "sat -tempinduct-baseonly -tempinduct-inductonly"
2015-02-21 17:53:22 +01:00
Clifford Wolf
dcbd00c101
Fixed basecase init for "sat -tempinduct"
2015-02-21 17:43:49 +01:00
Clifford Wolf
49dd9c713f
Fixed "flatten" for non-pre-derived modules
2015-02-21 15:01:13 +01:00
Clifford Wolf
4e6ca7760f
Replaced ezDefaultSAT with ezSatPtr
2015-02-21 12:15:41 +01:00
Clifford Wolf
f778a4081c
Catch constants assigned to cell outputs in "flatten"
2015-02-21 11:21:28 +01:00
Clifford Wolf
08c0fe164f
format fixes in "sat -dump_json"
2015-02-19 13:19:04 +01:00
Clifford Wolf
1ecee6c49c
Added "sat -dump_json" (WaveJSON format)
2015-02-19 10:53:40 +01:00
Clifford Wolf
20eb5cad4b
Changed "show" defaults for Win32
2015-02-19 09:11:38 +01:00
Clifford Wolf
f41378af8c
Fixed clang (svn trunk) warnings
2015-02-18 14:54:22 +01:00
Clifford Wolf
e4cf604ffd
Merge branch 'master' of github.com:cliffordwolf/yosys
2015-02-18 07:19:03 +01:00
Clifford Wolf
5f54be54b8
Added "select %xe %cie %coe"
2015-02-18 07:18:34 +01:00
Clifford Wolf
024aa559e2
wreduce help typo fix
2015-02-17 13:02:16 +01:00
Clifford Wolf
0748ef638d
Bugfix in wreduce
2015-02-16 09:08:00 +01:00
Clifford Wolf
0283703f9e
Added Viz to yosys.js
2015-02-15 22:53:41 +01:00
Clifford Wolf
40f021e136
Added "check -noinit"
2015-02-15 12:58:12 +01:00
Clifford Wolf
a54c994e2b
Cosmetic fixes in "hierarchy" for blackbox modules
2015-02-15 12:57:41 +01:00
Clifford Wolf
3216f9420e
More emscripten stuff, Added example app
2015-02-15 12:09:30 +01:00
Clifford Wolf
c6ae9ebb79
Fixed "stat" handling of blackbox modules
2015-02-14 22:36:34 +01:00
Clifford Wolf
e9368a1d7e
Various fixes for memories with offsets
2015-02-14 14:21:15 +01:00
Clifford Wolf
dcf2e24240
Added $meminit support to "memory" command
2015-02-14 12:55:03 +01:00
Clifford Wolf
910556560f
Added $meminit cell type
2015-02-14 10:23:03 +01:00
Clifford Wolf
a0a0594d1e
hotfix in "check" command
2015-02-13 14:40:49 +01:00
Clifford Wolf
04cb947d6a
Added "check" command
2015-02-13 14:34:51 +01:00
Clifford Wolf
d58c3eca3a
Some test related fixes
...
(incl. removal of three bad test cases)
2015-02-12 17:45:44 +01:00
Clifford Wolf
554a8df5e2
Added "proc_dlatch"
2015-02-12 16:56:01 +01:00
Clifford Wolf
87819c62fa
Less aggressive "share" defaults
2015-02-10 20:51:37 +01:00
Clifford Wolf
510deb3577
Added "scc -expect <N> -nofeedback"
2015-02-10 08:48:55 +01:00
Clifford Wolf
f889e3d385
Fixed iterator invalidation bug in "rename" command
2015-02-09 00:18:36 +01:00
Clifford Wolf
07afb14318
Fixed bug in "show -format .."
2015-02-08 23:29:54 +01:00
Clifford Wolf
bcd8a2fc56
Fixed eval_select_op() api
2015-02-08 19:06:16 +01:00
Clifford Wolf
09ee65a050
Added eval_select_args() and eval_select_op()
2015-02-08 18:56:06 +01:00
Clifford Wolf
5170b86108
Added equiv_add
2015-02-08 11:59:38 +01:00
Clifford Wolf
d5e30978e9
Added "select -read"
2015-02-06 10:01:22 +01:00
Clifford Wolf
a038787c9b
Added onehot attribute
2015-02-04 18:52:54 +01:00
Clifford Wolf
8805c24640
Fixed opt_clean performance bug
2015-02-04 16:34:06 +01:00
Clifford Wolf
a8f4a099b5
Using design->selected_modules() in opt_*
2015-02-03 23:45:01 +01:00
Clifford Wolf
6eb34038f4
Merge pull request #48 from rubund/master
...
Fixed typos found by lintian
2015-02-01 22:55:52 +01:00
Clifford Wolf
893fe87a33
Improved performance in equiv_simple
2015-02-01 22:50:48 +01:00
Ruben Undheim
49649d6ef0
Fixed typos found by lintian
2015-02-01 21:49:55 +01:00
Clifford Wolf
9abbeefe6e
Using selections in "ls" command
2015-02-01 00:13:19 +01:00
Clifford Wolf
8dfa105255
Bugfix in opt_const $eq -> buffer code
2015-01-31 23:25:32 +01:00
Clifford Wolf
1d92915a55
Fixed equiv_make for partially undriven nets (e.g. after "clean -purge")
2015-01-31 21:07:42 +01:00
Clifford Wolf
bc86b4a7e9
Added "equiv_induct -undef"
2015-01-31 13:58:04 +01:00
Clifford Wolf
e9cfc4a453
Added "equiv_simple -undef"
2015-01-31 13:06:41 +01:00
Clifford Wolf
f80f5b721d
Added "equiv_make -blacklist <file> -encfile <file>"
2015-01-31 12:08:20 +01:00
Clifford Wolf
bedd46338f
Added "fsm -encfile"
2015-01-30 22:46:53 +01:00
Clifford Wolf
9ebf803cbe
Improved an error message
2015-01-28 00:46:00 +01:00
Clifford Wolf
df64542288
Fixed bug in equiv_miter
2015-01-28 00:34:30 +01:00
Clifford Wolf
23e54bda81
Added "sat -show-ports"
2015-01-27 23:04:28 +00:00
Clifford Wolf
13b50bacfe
Rethrow with "catch(...) throw;"
2015-01-25 22:57:09 +01:00
Clifford Wolf
acfaeb8d34
Added equiv_remove
2015-01-25 14:20:22 +01:00
Clifford Wolf
66a6b86daa
Added equiv_miter
2015-01-25 14:00:49 +01:00
Clifford Wolf
2a9ad48eb6
Added ENABLE_NDEBUG makefile options
2015-01-24 12:16:46 +01:00
Clifford Wolf
75bbeb828a
Various equiv_* improvements
2015-01-24 00:32:24 +01:00
Clifford Wolf
43951099cf
Added dict/pool.sort()
2015-01-24 00:13:27 +01:00
Clifford Wolf
1cb4c925d0
Improvements in equiv_make, equiv_induct
2015-01-22 21:23:01 +01:00
Clifford Wolf
5707ba22c1
Improved xdot calling
2015-01-22 20:45:53 +01:00
Clifford Wolf
f6d94e8720
Added equiv_induct
2015-01-22 14:03:18 +01:00
Clifford Wolf
a6aa32e762
Various equiv_simple improvements
2015-01-22 13:42:04 +01:00
Clifford Wolf
0a225f8b27
Moved equiv stuff to passes/equiv/
2015-01-22 12:03:15 +01:00
Clifford Wolf
abf8398216
Progress in equiv_simple
2015-01-21 23:59:58 +00:00
Clifford Wolf
74e1de1fac
Fixed opt_muxtree performance bug
2015-01-21 16:44:07 +01:00
Clifford Wolf
5febbe3620
Added equiv_simple
2015-01-19 15:08:44 +01:00
Clifford Wolf
615c2e136e
Added equiv_status
2015-01-19 14:20:04 +01:00
Clifford Wolf
76c5d863c5
Added equiv_make command
2015-01-19 13:59:08 +01:00
Clifford Wolf
8d295730e5
Refactoring of memory_bram and xilinx brams
2015-01-18 19:05:29 +01:00
Clifford Wolf
f630868bc9
Improvements in opt_muxtree
2015-01-18 12:57:36 +01:00
Clifford Wolf
d3b35017f8
More opt_muxtree cleanups
2015-01-18 12:13:18 +01:00
Clifford Wolf
61192514e3
Various cleanups and improvements in opt_muxtree
2015-01-18 11:17:56 +01:00
Clifford Wolf
8658eed52a
Added support for memories to flatten (techmap)
2015-01-17 20:46:52 +01:00
Clifford Wolf
a95c229e12
Fixed a bug in opt_muxtree for "mux forests"
2015-01-17 13:56:53 +01:00
Clifford Wolf
3628ca989c
Improved opt_muxtree
2015-01-17 12:05:19 +01:00
Clifford Wolf
8ce8a230f4
Bugfix in dff2dffe
2015-01-16 17:51:17 +01:00
Clifford Wolf
2e36faeced
Added "abc -lut w1:w2"
2015-01-15 13:37:48 +01:00
Clifford Wolf
9065fb25cc
Fixed handling of foo.__TECHMAP_...
2015-01-15 13:36:57 +01:00
Clifford Wolf
8426884b40
Re-enabled mux->and/or transform (and fixed lm32 in yosys-bigsim)
2015-01-13 13:20:09 +01:00
Clifford Wolf
95f1eb9b87
Only enable code coverage counters on linux
2015-01-09 17:32:53 +01:00
Clifford Wolf
fd787609aa
disabled problematic mux -> and/or transform
2015-01-07 23:25:51 +01:00
Clifford Wolf
b26590f8ab
memory_bram hotfix for memories with width 1
2015-01-06 23:59:53 +01:00
Clifford Wolf
da72050107
removed old debug code
2015-01-06 16:08:04 +01:00
Clifford Wolf
9474928672
Towards Xilinx bram support
2015-01-06 15:26:33 +01:00
Clifford Wolf
4a0b3a5423
Various small improvements to synth_xilinx
2015-01-06 14:37:50 +01:00
Clifford Wolf
081e1a49f8
Towards Xilinx bram support
2015-01-06 14:26:51 +01:00
Clifford Wolf
462b22f44f
dict<> ref vs insert bugfix
2015-01-06 00:16:44 +01:00
Clifford Wolf
9ea2511fe8
Towards Xilinx bram support
2015-01-05 13:59:04 +01:00
Clifford Wolf
8898897f7b
Towards Xilinx bram support
2015-01-04 14:23:30 +01:00
Clifford Wolf
daae35319b
Added memory_bram "shuffle_enable" feature
2015-01-04 13:14:30 +01:00
Clifford Wolf
5d631f0ea7
Removed left over debug code from memory_bram
2015-01-04 11:46:04 +01:00
Clifford Wolf
0648e2874c
Fixed pattern matching in "hierarchy -generate"
2015-01-04 11:45:39 +01:00
Clifford Wolf
45918b8315
Added "memory -bram"
2015-01-03 17:40:20 +01:00
Clifford Wolf
a7fe87f888
Added memory_bram 'or_next_if_better' feature
2015-01-03 17:34:05 +01:00
Clifford Wolf
fd2c224c04
memory_bram transp support
2015-01-03 12:41:46 +01:00
Clifford Wolf
a7e43ae3d9
Progress in memory_bram
2015-01-03 10:57:01 +01:00
Clifford Wolf
90f4017703
Added proper clkpol support to memory_bram
2015-01-02 22:57:08 +01:00
Clifford Wolf
bbf89c4dc6
Progress in memory_bram
2015-01-02 13:59:47 +01:00
Clifford Wolf
36c20f2ede
Progress in memory_bram
2015-01-02 00:07:44 +01:00
Clifford Wolf
f29f4e7c83
Progress in memory_bram
2015-01-01 15:32:37 +01:00
Clifford Wolf
17c1c55473
Progress in memory_bram
2015-01-01 12:17:19 +01:00
Clifford Wolf
e62d838bd4
Removed SigSpec::extend_xx() api
2015-01-01 11:41:52 +01:00
Clifford Wolf
327a5d42b6
Progress in memory_bram
2014-12-31 22:50:08 +01:00
Clifford Wolf
94e6b70736
Added memory_bram (not functional yet)
2014-12-31 16:53:53 +01:00
Clifford Wolf
11c3b81c08
typo fix for "opt -fast"
2014-12-30 22:35:38 +01:00
Clifford Wolf
972faab1c8
Fixed a bug in "select %ci %co %x"
2014-12-30 20:15:18 +01:00
Clifford Wolf
4606addfef
Fixed typo in ABC command
2014-12-30 19:38:40 +01:00
Clifford Wolf
c64b1de11d
Fixed build with SMALL=1
2014-12-30 11:41:24 +01:00
Clifford Wolf
ed8f1b42fc
Fixed memory corruption in "splice" command
2014-12-29 20:23:22 +01:00
Clifford Wolf
29a555ec7e
Added statehash to ezSAT
2014-12-29 17:10:37 +01:00
Clifford Wolf
7a4d5d1c0f
Less verbose ABC output
2014-12-29 15:17:40 +01:00
Clifford Wolf
3ff0d04555
Cleanups in opt_clean
2014-12-29 05:11:06 +01:00
Clifford Wolf
7d843adef9
dict/pool changes in opt_clean
2014-12-29 04:06:52 +01:00
Clifford Wolf
cfe0817697
Converting "share" to dict<> and pool<> complete
2014-12-29 02:01:42 +01:00
Clifford Wolf
9ff3a9f30d
Switched most of "share" to dict<> and pool<>
2014-12-29 00:42:48 +01:00
Clifford Wolf
445686cba3
using dict and pool in opt_reduce
2014-12-28 21:27:05 +01:00
Clifford Wolf
951c72ba52
bugfix in opt_share
2014-12-28 21:26:36 +01:00
Clifford Wolf
3da46d3437
Renamed hashmap.h to hashlib.h, some related improvements
2014-12-28 17:51:16 +01:00
Clifford Wolf
6c8b0a5fd1
More dict/pool related changes
2014-12-27 12:02:57 +01:00
Clifford Wolf
66ab88d7b0
More hashtable finetuning
2014-12-27 03:04:50 +01:00
Clifford Wolf
ec4751e55c
Replaced std::unordered_set (nodict) with Yosys::pool
2014-12-26 21:59:41 +01:00
Clifford Wolf
9e6fb0b02c
Replaced std::unordered_map as implementation for Yosys::dict
2014-12-26 21:35:22 +01:00
Clifford Wolf
a6c96b986b
Added Yosys::{dict,nodict,vector} container types
2014-12-26 10:53:21 +01:00
Clifford Wolf
b748622a7f
Added "test_cell -muxdiv"
2014-12-25 19:22:39 +01:00
Clifford Wolf
7dece74fae
Added "test_cell -w" feature
2014-12-25 17:04:13 +01:00
Clifford Wolf
170788a3de
Fixed simplemap for $ne cells with output width > 1
2014-12-25 16:41:20 +01:00
Clifford Wolf
b6a7e21d2e
Fixed off-by-one bug in "hierarchy -check" for positional module args
2014-12-24 16:26:18 +01:00
Clifford Wolf
aad195b88c
Added "dfflibmap -prepare" help
2014-12-24 12:56:05 +01:00
Clifford Wolf
35f5aa300f
Added "dfflibmap -prepare"
2014-12-24 12:19:20 +01:00
Clifford Wolf
032ce573a3
Added "dff2dffe -direct" for direct gate mapping
2014-12-24 11:39:15 +01:00
Clifford Wolf
8c1a72c2a4
Added "dff2dffe -unmap"
2014-12-24 11:09:01 +01:00
Clifford Wolf
afcacd6437
Added support for gate-level cells in dff2dffe
2014-12-24 10:49:54 +01:00
Clifford Wolf
4aa9fbbf3f
Improvements in simplemap api, added $ne $nex $eq $eqx support
2014-12-24 10:49:24 +01:00
Clifford Wolf
edb3c9d0c4
Renamed extend() to extend_xx(), changed most users to extend_u0()
2014-12-24 09:51:17 +01:00
Clifford Wolf
48ca1ff9ef
Improved ABC clock domain partitioning
2014-12-23 14:08:38 +01:00
Clifford Wolf
5fe02b7965
Indenting fix in show.cc
2014-12-23 13:49:54 +01:00
Clifford Wolf
4f5b97954e
Added "show -colorattr"
2014-12-23 12:29:29 +01:00
Clifford Wolf
a216df0433
Added "abc -markgroups"
2014-12-23 12:29:02 +01:00
Clifford Wolf
76fa527492
Added support for multiple clock domains to "abc" pass
2014-12-21 16:52:05 +01:00
Clifford Wolf
25844b5683
Fixed "abc" pass for clk and enable signals driven by logic
2014-12-21 11:13:25 +01:00
Clifford Wolf
f7b323196f
Added DFFE support to "abc" pass
2014-12-20 00:44:03 +01:00
Clifford Wolf
bacd3699b3
Checking existence of ports in "hierarchy -check"
2014-12-19 18:47:19 +01:00
Clifford Wolf
032511fac8
Added functionality to dff2dffe pass
2014-12-08 15:38:58 +01:00
Clifford Wolf
97487fee32
Added skeleton dff2dffe pass
2014-12-08 14:10:52 +01:00
Clifford Wolf
f1764b4fe9
Added $dffe cell type
2014-12-08 10:50:19 +01:00
Clifford Wolf
51cfcd8331
Fixed bug in "hierarchy -top" with array of instances
2014-11-27 12:47:33 +01:00
Clifford Wolf
a112b10934
Introducing YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
2014-11-09 10:55:04 +01:00
Clifford Wolf
fe829bdbdc
Added log_warning() API
2014-11-09 10:44:23 +01:00
Clifford Wolf
d92fb5b35e
Added missing fixup_ports() calls to "rename" command
2014-11-08 12:38:48 +01:00
Clifford Wolf
420bc05627
Added "Nx" syntax to "show" command for repeating SigChunks
2014-11-08 10:58:57 +01:00
Clifford Wolf
546e8b5fe7
Improved TopoSort determinism
2014-11-07 15:21:03 +01:00
Clifford Wolf
99cdfb3110
Fixed typo in "log_cmd_error_exception"
2014-11-07 12:48:15 +01:00
Clifford Wolf
a346c0bf2b
Made "cover" a compile-time option (disabled by default)
2014-11-06 09:39:55 +01:00
Clifford Wolf
ab28491f27
Added "opt -full" alias for all more aggressive optimizations
2014-10-31 03:36:51 +01:00
Clifford Wolf
c5eb5e56b8
Re-introduced Yosys::readsome() helper function
...
(f.read() + f.gcount() made problems with lines > 16kB)
2014-10-23 10:58:36 +02:00
Clifford Wolf
bb631c6f5c
Also look for yosys-abc in parent dir on win32
2014-10-18 19:01:44 +02:00
Clifford Wolf
41db98ba31
Fixed typo in test_cell
2014-10-18 16:52:06 +01:00
Clifford Wolf
84ffe04075
Fixed various VS warnings
2014-10-18 15:20:38 +02:00
Clifford Wolf
468ae92374
Various win32 / vs build fixes
2014-10-17 14:01:47 +02:00
Clifford Wolf
973d376733
Added genfiles.zip to MXE "make dist"
2014-10-17 12:11:15 +02:00
Clifford Wolf
4df902637a
Various MXE build fixes
2014-10-17 12:04:40 +02:00
William Speirs
31267a1ae8
Header changes so it will compile on VS
2014-10-17 11:41:36 +02:00
Clifford Wolf
18cb8b4636
Don't be too smart with $dff cells with "init" attribute on out signal
2014-10-16 11:49:31 +02:00
Clifford Wolf
66eb254fc2
Some cleanups in opt_clean
2014-10-16 11:46:57 +02:00
Clifford Wolf
c3e9922b5d
Replaced readsome() with read() and gcount()
2014-10-15 01:12:53 +02:00
William Speirs
e5b8390f44
Changed from "and" to "&&"
2014-10-15 00:59:22 +02:00
William Speirs
6433203b39
Wrapped init in std::set constructor
2014-10-15 00:58:05 +02:00
Clifford Wolf
c21c9dab1e
Removed CHECK() macro from libparse.cc (was using non-std c features)
2014-10-13 17:22:06 +02:00
Clifford Wolf
0913e968f5
More win32/abc fixes
2014-10-12 14:48:19 +02:00
Clifford Wolf
0b9282a779
Added make_temp_{file,dir}() and remove_directory() APIs
2014-10-12 12:11:57 +02:00
Clifford Wolf
9b4d171e37
Using stringf() instead of asprintf() in "abc" pass
2014-10-12 11:17:53 +02:00
Clifford Wolf
b1596bc0e7
Added run_command() api to replace system() and popen()
2014-10-12 10:57:15 +02:00
Clifford Wolf
d2b8b48bf3
Renamed "log.cc" to "logcmd.cc" so there aren't two "log.cc" in the source tree
2014-10-11 12:13:46 +02:00
Clifford Wolf
35fbc0b35f
Do not the 'z' modifier in format string (another win32 fix)
2014-10-11 11:42:08 +02:00
Clifford Wolf
8263f6a74a
Fixed win32 troubles with f.readsome()
2014-10-11 11:36:22 +02:00
Clifford Wolf
51b1824979
Disabled "cover -d" on win32
2014-10-11 10:49:43 +02:00
Clifford Wolf
54bf3a95dd
More Win32 build fixes
2014-10-10 18:34:19 +02:00
Clifford Wolf
ee5165c6e4
Moved patmatch() to yosys.cc
2014-10-10 18:20:17 +02:00
Clifford Wolf
774933a0d8
Replaced fnmatch() with patmatch()
2014-10-10 18:02:17 +02:00
Clifford Wolf
bbd808072b
Added format __attribute__ to stringf()
2014-10-10 17:22:08 +02:00
Clifford Wolf
7cb0d3aa1a
Renamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because of name collision on Win32
2014-10-10 17:07:24 +02:00
Clifford Wolf
4569a747f8
Renamed SIZE() to GetSize() because of name collision on Win32
2014-10-10 17:07:24 +02:00
Clifford Wolf
fea11f0fa4
Added API for generic cell cost calculations
2014-10-09 13:59:26 +02:00
Clifford Wolf
ccf7b2e342
Added mxe-based cross build for win32
2014-10-09 10:50:44 +02:00
Clifford Wolf
696d7ed40e
Fixes in "hilomap" help message
2014-10-08 21:38:37 +02:00
Clifford Wolf
9dea161321
sort cell types in "stat" output by name
2014-10-03 19:21:04 +02:00
Clifford Wolf
c5c7066ea6
sat encoding for exclusive $pmux ctrl inputs in "share" pass
2014-10-03 19:01:24 +02:00
Clifford Wolf
3e4b0cac8d
added resource sharing of $macc cells
2014-10-03 12:58:40 +02:00
Clifford Wolf
c3e779a65f
Added $_BUF_ cell type
2014-10-03 10:12:28 +02:00
Clifford Wolf
600c6cb013
remove buffers in opt_clean
2014-10-03 10:04:15 +02:00
Clifford Wolf
7019bc00e4
resource sharing of $alu cells
2014-10-03 09:55:50 +02:00
Clifford Wolf
2ee03f5da4
set "keep" on modules with $assert cells in "hierarchy"
2014-09-30 19:16:40 +02:00
Clifford Wolf
0b8cfbc6fd
Added support for "keep" on modules
2014-09-29 12:51:54 +02:00
Clifford Wolf
f9a307a50b
namespace Yosys
2014-09-27 16:17:53 +02:00
Clifford Wolf
13117bb346
Re-enabled assert for new logic loops in "share" pass
2014-09-21 19:44:08 +02:00
Clifford Wolf
96e821dc6c
Various improvements regarding logic loops in "share" results
2014-09-21 19:36:56 +02:00
Clifford Wolf
d6e2ace95b
Logic loop bugfix for "share" pass
2014-09-21 15:13:44 +02:00
Clifford Wolf
b28be0759f
Added "share -limit"
2014-09-21 15:13:06 +02:00
Clifford Wolf
a6c08b40fe
Still loop bug in "share": changed assert to warning
2014-09-21 14:51:07 +02:00
Clifford Wolf
8d60754aef
Do not introduce new logic loops in "share"
2014-09-21 13:52:39 +02:00
Clifford Wolf
edf11c635a
Assert on new logic loops in "share" pass
2014-09-21 12:57:33 +02:00
Clifford Wolf
a7758ef953
Added "test_abcloop" command
2014-09-19 15:51:34 +02:00
Clifford Wolf
5827826098
Small improvements in "abc" command handle_loops() function
2014-09-19 14:05:41 +02:00
Clifford Wolf
3aa003c8e9
Using "NOT" instead of "INV" as cell name in default abc genlib file
2014-09-19 13:15:31 +02:00
Clifford Wolf
f7bb8f244b
Alphabetically sort port names in "show" output
2014-09-19 11:13:10 +02:00
Clifford Wolf
f56b92818b
Do not run "scorr" in "abc -fast"
2014-09-18 19:00:21 +02:00
Clifford Wolf
815fab9d71
Added "abc -fast"
2014-09-18 12:57:37 +02:00
Clifford Wolf
9ae559b990
Fixed $_NOR vs. $_NOR_ typo in abc.cc
2014-09-16 12:45:05 +02:00
Clifford Wolf
ae02d9cb9a
Fixed $memwr/$memrd order in memory_dff
2014-09-16 12:40:58 +02:00
Clifford Wolf
b86410b2ab
More aggressive $macc merging in alumacc
2014-09-15 12:42:11 +02:00
Clifford Wolf
b470c480e9
Added the obvious optimizations to alumacc $macc generator
2014-09-15 12:22:03 +02:00
Clifford Wolf
fcbda07411
Improved maccmap tree bit packing
2014-09-15 12:00:19 +02:00
Clifford Wolf
2cbdbaad1f
Fixed wreduce $shiftx handling
2014-09-15 11:29:09 +02:00
Clifford Wolf
7e156a5419
Fixed techmap_wrap for techmap_celltype
2014-09-14 15:34:36 +02:00
Clifford Wolf
014bb34e0e
Various fixes/cleanups in alumacc and maccmap
2014-09-14 14:49:53 +02:00
Clifford Wolf
124e759280
Added techmap_wrap attribute
2014-09-14 14:49:26 +02:00
Clifford Wolf
b34ca15185
alumacc fix for $pos cells
2014-09-14 14:00:14 +02:00
Clifford Wolf
0df1d9ad72
Extract $alu cells in alumacc
2014-09-14 13:23:44 +02:00
Clifford Wolf
7b16c63101
Merge $macc cells in alumacc pass
2014-09-14 11:21:37 +02:00
Clifford Wolf
0b72f0acb1
Basic $macc extract in alumacc
2014-09-14 10:45:28 +02:00
Clifford Wolf
ff157fb74f
alumacc skeleton
2014-09-14 10:02:00 +02:00
Clifford Wolf
aab0e3bf70
Cleanup in wreduce
2014-09-14 10:01:30 +02:00
Clifford Wolf
af0c8873bb
Added $lcu cell type
2014-09-08 13:31:04 +02:00
Clifford Wolf
d46bac3305
Added "$fa" cell type
2014-09-08 12:15:39 +02:00
Clifford Wolf
1a88e47396
Trim msb/lsb zero bits from full adder in maccmap
2014-09-08 11:21:58 +02:00
Clifford Wolf
6747a7047e
Added "test_cell -const"
2014-09-08 11:12:39 +02:00
Clifford Wolf
c50b841b29
Added 'techmap_maccmap' techmap attribute
2014-09-07 18:23:37 +02:00
Clifford Wolf
015dcdc84c
Added "maccmap" command
2014-09-07 18:23:04 +02:00
Clifford Wolf
15b3c54fea
Added "test_cell -nosat"
2014-09-07 17:05:41 +02:00
Clifford Wolf
9329a76818
Various bug fixes (related to $macc model testing)
2014-09-06 20:30:46 +02:00
Clifford Wolf
fa64942018
Added $macc SAT model
2014-09-06 19:44:11 +02:00
Clifford Wolf
b847ec8a0b
Added $macc cell type
2014-09-06 15:47:46 +02:00
Clifford Wolf
34af6a1303
Merge branch 'master' of github.com:cliffordwolf/yosys
2014-09-06 11:46:44 +02:00
Clifford Wolf
e1743b3bac
Added "test_cell -script"
2014-09-06 11:46:07 +02:00
Ruben Undheim
79cbf9067c
Corrected spelling mistakes found by lintian
2014-09-06 08:47:06 +02:00
Clifford Wolf
f5a40e7043
Fixed "opt_const -fine" for $pos cells
2014-09-04 08:55:58 +02:00
Clifford Wolf
8927aa6148
Removed $bu0 cell type
2014-09-04 02:07:52 +02:00
Clifford Wolf
5733f4a39d
Fixed "test_cells -vlog"
2014-09-03 13:43:37 +02:00
Clifford Wolf
f1869667ca
Improvements in "test_cell -vlog"
2014-09-02 23:21:15 +02:00
Clifford Wolf
66bf2bb92e
Added test_cell -vlog
2014-09-02 22:49:43 +02:00
Clifford Wolf
acd7a99aef
Added SAT testing to test_cell eval stage
2014-09-02 17:28:13 +02:00
Clifford Wolf
37fe7c7bdf
Removed references to yosys-svgviewer from docs
2014-09-02 04:03:06 +02:00
Clifford Wolf
9f00a0cd2d
Using "xdot" instead of "yosys-svgviewer" in show command
2014-09-02 03:28:46 +02:00
Clifford Wolf
630befdf6d
Added $alu support to test_cell
2014-09-01 16:36:04 +02:00
Clifford Wolf
c7f81e4e49
Added "test_cell -simlib -v"
2014-09-01 15:37:21 +02:00
Clifford Wolf
826fdb34d8
Added "techmap -autoproc"
2014-09-01 15:36:29 +02:00
Clifford Wolf
27a1bfbec6
Fixes in old SAT example.ys
2014-09-01 11:45:47 +02:00
Clifford Wolf
d5148f2e01
Moved "share" and "wreduce" to passes/opt/
2014-09-01 11:45:26 +02:00
Clifford Wolf
e07698818d
Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data
2014-09-01 11:36:02 +02:00
Clifford Wolf
e3664066d5
Added eval testing to test_cell
2014-08-31 18:08:42 +02:00
Clifford Wolf
8649b57b6f
Added $lut support in test_cell, techmap, satgen
2014-08-31 17:43:31 +02:00
Clifford Wolf
2a1b08aeb3
Added design->scratchpad
2014-08-30 19:37:12 +02:00
Clifford Wolf
6ff46323a3
Improved write address decoder generation memory_map
2014-08-30 18:18:15 +02:00
Clifford Wolf
66763fad4e
Using worker class in memory_map
2014-08-30 17:39:08 +02:00
Clifford Wolf
3a7d5d188d
Don't change existing binary FSM encoding if it is already optimal
2014-08-30 14:43:06 +02:00
Clifford Wolf
f910481f35
Using $pmux info in fsm_extract to optimize transition ctrl_in patterns
2014-08-30 14:34:49 +02:00
Clifford Wolf
ab019b0bd5
Improved handling of $pmux cells in fsm_extract
2014-08-30 14:11:57 +02:00
Clifford Wolf
d148b0af0d
Fixed inserting of Q-inverters in dfflibmap
2014-08-27 19:44:12 +02:00
Clifford Wolf
084685f480
Implemented "rename -enumerate -pattern"
2014-08-26 12:51:08 +02:00
Clifford Wolf
7bbbe3580d
Optimize shift ops with constant rhs in opt_const
2014-08-24 17:08:43 +02:00
Clifford Wolf
641501203c
Added some additional log messages to opt_const
2014-08-24 17:08:43 +02:00
Clifford Wolf
9c5a63c52c
azonenberg: Make dump_vcd save model when temporal induction fails due to step limit
2014-08-24 13:27:40 +02:00
Clifford Wolf
c642dd0b3e
Only call proc_share_dirname() in techmap when necessary
2014-08-23 15:32:00 +02:00
Clifford Wolf
19cff41eb4
Changed frontend-api from FILE to std::istream
2014-08-23 15:03:55 +02:00
Clifford Wolf
5dce303a2a
Changed backend-api from FILE to std::ostream
2014-08-23 13:54:21 +02:00
Clifford Wolf
fff12c719f
Added "stat -width"
2014-08-22 17:20:28 +02:00
Clifford Wolf
98442e019d
Added emscripten (emcc) support to build system and some build fixes
2014-08-22 16:20:22 +02:00
Clifford Wolf
a3494fa9ed
Added "plugin" command
2014-08-22 14:00:11 +02:00
Clifford Wolf
410d043dd8
Renamed toposort.h to utils.h
2014-08-17 00:55:35 +02:00
Clifford Wolf
7f734ecc09
Added module->uniquify()
2014-08-16 23:50:36 +02:00
Clifford Wolf
3b9157f9a6
Added "test_cell -s <seed>"
2014-08-16 19:44:31 +02:00
Clifford Wolf
47c2637a96
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
2014-08-16 18:29:39 +02:00
Clifford Wolf
eb17fbade5
Added "opt -fast"
2014-08-16 15:34:15 +02:00
Clifford Wolf
674f421b47
Bugfix in iopadmap
2014-08-15 14:29:42 +02:00
Clifford Wolf
b64b38eea2
Renamed $lut ports to follow A-Y naming scheme
2014-08-15 14:18:40 +02:00
Clifford Wolf
f092b50148
Renamed $_INV_ cell type to $_NOT_
2014-08-15 14:11:40 +02:00
Clifford Wolf
ca87116449
More idstring sort_by_* helpers and fixed tpl ordering in techmap
2014-08-15 02:40:46 +02:00
Clifford Wolf
d320e75087
document "techmap -map %<design-name>"
2014-08-15 02:01:30 +02:00
Clifford Wolf
1bf7a18fec
Added module->ports
2014-08-14 16:22:52 +02:00
Clifford Wolf
13f2f36884
RIP $safe_pmux
2014-08-14 11:39:46 +02:00
Clifford Wolf
28cf48e31f
Some improvements in FSM mapping and recoding
2014-08-14 11:22:45 +02:00
Clifford Wolf
996c06f64d
Added "abc -D" for setting delay target
2014-08-14 11:05:25 +02:00
Clifford Wolf
28bc7aeb93
Filter ANSI escape sequences from ABC output
2014-08-13 13:40:29 +02:00
Clifford Wolf
9d353fc543
Fixed handling of constant-true branches in proc_clean
2014-08-12 17:35:22 +02:00
Clifford Wolf
788bd02f97
Fixed FSM mapping for multiple reset-like signals
2014-08-10 12:04:02 +02:00
Clifford Wolf
9d4362990f
Fixed "share" for complex scenarios with never-active cells
2014-08-09 17:07:20 +02:00
Clifford Wolf
b9811d5aff
Do not share any $reduce_* cells (its complicated and not worth it anyways)
2014-08-09 15:40:25 +02:00
Clifford Wolf
2faef89738
Some improvements in fsm_opt and fsm_map for FSM with unreachable states
2014-08-09 14:49:51 +02:00
Clifford Wolf
58ac605470
Another fsm_extract bugfix
2014-08-08 14:56:04 +02:00
Clifford Wolf
7067c43ec0
Fixed "fsm -export"
2014-08-08 14:56:03 +02:00
Clifford Wolf
cb6ca08a53
Fixed sharing of reduce operator
2014-08-08 14:24:09 +02:00
Clifford Wolf
7c94024fc3
Fixed fsm_extract for wreduced muxes
2014-08-08 13:47:20 +02:00
Clifford Wolf
622ebab671
Added "sat -prove-skip"
2014-08-08 13:11:54 +02:00
Clifford Wolf
0b8b8d41eb
Fixed build with gcc-4.6
2014-08-07 22:37:01 +02:00
Clifford Wolf
c55eb8f8a6
Use "-keepdc" in "miter -equiv -flatten"
2014-08-07 16:42:35 +02:00
Clifford Wolf
b4f10e342c
Various improvements in memory_dff pass
2014-08-06 14:31:38 +02:00
Clifford Wolf
2501abe1ee
Various fixes and improvements in wreduce pass
2014-08-05 19:01:41 +02:00
Clifford Wolf
5b3dc07b9a
Removed old "constmap" from wreduce code
2014-08-05 16:53:53 +02:00
Clifford Wolf
523df73145
Added support for truncating of wires to wreduce pass
2014-08-05 14:47:03 +02:00
Clifford Wolf
d3b1a29708
Cleanups and improvements in wreduce pass
2014-08-05 13:11:04 +02:00
Clifford Wolf
1c182cedb7
Added mux support to wreduce command
2014-08-05 12:49:53 +02:00
Clifford Wolf
0bb6942218
Added "show -signed"
2014-08-04 15:40:08 +02:00
Clifford Wolf
ebbbe7fc83
Added RTLIL::IdString::in(...)
2014-08-04 15:40:07 +02:00
Clifford Wolf
c7f99be3be
Fixed "share" for memory read ports
2014-08-03 20:22:33 +02:00
Clifford Wolf
027376515a
Progress in "wreduce" pass
2014-08-03 20:02:42 +02:00
Clifford Wolf
0b02f6ca30
Added "wreduce" command (work in progress)
2014-08-03 15:02:05 +02:00
Clifford Wolf
014a41fcf3
Implemented recursive techmap
2014-08-03 12:40:43 +02:00
Clifford Wolf
9bb5298c10
Fixes in show command (related to new IdString)
2014-08-03 12:40:23 +02:00
Clifford Wolf
08ec33a5e5
Implemented simplemap support for "techmap -extern"
2014-08-02 21:55:13 +02:00
Clifford Wolf
b6acbc82e6
Bugfix in "techmap -extern"
2014-08-02 20:54:30 +02:00
Clifford Wolf
8e7361f128
Removed at() method from RTLIL::IdString
2014-08-02 19:08:02 +02:00
Clifford Wolf
04727c7e0f
No implicit conversion from IdString to anything else
2014-08-02 18:58:40 +02:00
Clifford Wolf
768eb846c4
More bugfixes related to new RTLIL::IdString
2014-08-02 18:14:21 +02:00
Clifford Wolf
8fd1c269ac
Fixed a performance bug in opt_reduce
2014-08-02 15:12:16 +02:00
Clifford Wolf
b9bd22b8c8
More cleanups related to RTLIL::IdString usage
2014-08-02 13:19:57 +02:00
Clifford Wolf
14412e6c95
Preparations for RTLIL::IdString redesign: cleanup of existing code
2014-08-02 00:45:25 +02:00
Clifford Wolf
bd74ed7da4
Replaced sha1 implementation
2014-08-01 19:01:10 +02:00
Clifford Wolf
d13eb7e099
Added ModIndex helper class, some changes to RTLIL::Monitor
2014-08-01 17:14:32 +02:00
Clifford Wolf
03ef9a75c6
Added "test_autotb -n <num_iter>" option
2014-08-01 03:55:51 +02:00
Clifford Wolf
32a1cc3efd
Renamed modwalker.h to modtools.h
2014-07-31 23:30:18 +02:00
Clifford Wolf
cdae8abe16
Renamed port access function on RTLIL::Cell, added param access functions
2014-07-31 16:38:54 +02:00
Clifford Wolf
b5a9e51b96
Added "trace" command
2014-07-31 15:02:16 +02:00
Clifford Wolf
e6d33513a5
Added module->design and cell->module, wire->module pointers
2014-07-31 14:11:39 +02:00
Clifford Wolf
1cb25c05b3
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
2014-07-31 13:19:47 +02:00
Clifford Wolf
1202f7aa4b
Renamed "stdcells.v" to "techmap.v"
2014-07-31 02:32:00 +02:00
Clifford Wolf
6ca0c569d9
Added "techmap -assert"
2014-07-31 02:21:41 +02:00
Clifford Wolf
2541489105
Added techmap CONSTMAP feature
2014-07-30 22:04:30 +02:00
Clifford Wolf
6400ae3648
Added write_file command
2014-07-30 19:59:29 +02:00
Clifford Wolf
ceecf5b153
Improvements in test_cell
2014-07-30 18:49:12 +02:00
Clifford Wolf
273383692a
Added "test_cell" command
2014-07-29 22:07:41 +02:00
Clifford Wolf
e6df25bf74
Renamed "write_autotest" to "test_autotb" and moved to passes/tests/
2014-07-29 21:12:50 +02:00
Clifford Wolf
77e2d39cd0
Allow "hierarchy -generate" for $__ cells
2014-07-29 16:35:13 +02:00
Clifford Wolf
03c96f9ce7
Added "techmap -map %{design-name}"
2014-07-29 16:35:13 +02:00
Clifford Wolf
397b00252d
Added $shift and $shiftx cell types (needed for correct part select behavior)
2014-07-29 16:35:13 +02:00
Clifford Wolf
7bd2d1064f
Using log_assert() instead of assert()
2014-07-28 11:27:48 +02:00
Clifford Wolf
8b0f50792c
Added techmap -extern
2014-07-27 21:31:18 +02:00
Clifford Wolf
5da343b7de
Added topological sorting to techmap
2014-07-27 16:43:39 +02:00
Clifford Wolf
0c86d6106c
Added SigPool::check(bit)
2014-07-27 15:38:02 +02:00
Clifford Wolf
77a1462f2d
Fixed bug in opt_clean
2014-07-27 15:13:29 +02:00
Clifford Wolf
d07a871d35
Improved performance of opt_const on large modules
2014-07-27 14:50:25 +02:00
Clifford Wolf
dbb3556e3f
Fixed a bug in opt_clean and some RTLIL API usage cleanups
2014-07-27 13:19:05 +02:00
Clifford Wolf
d878fcbdc7
Added log_cmd_error_expection
2014-07-27 12:05:50 +02:00
Clifford Wolf
49f72421d5
Using new obj iterator API in a few places
2014-07-27 11:32:42 +02:00
Clifford Wolf
10e5791c5e
Refactoring: Renamed RTLIL::Design::modules to modules_
2014-07-27 11:18:30 +02:00
Clifford Wolf
4c4b602156
Refactoring: Renamed RTLIL::Module::cells to cells_
2014-07-27 01:51:45 +02:00
Clifford Wolf
f9946232ad
Refactoring: Renamed RTLIL::Module::wires to wires_
2014-07-27 01:49:51 +02:00
Clifford Wolf
d68c993ed2
Changed more code to the new RTLIL::Wire constructors
2014-07-26 21:30:38 +02:00
Clifford Wolf
946ddff9ce
Changed a lot of code to the new RTLIL::Wire constructors
2014-07-26 20:12:50 +02:00
Clifford Wolf
3f4e3ca8ad
More RTLIL::Cell API usage cleanups
2014-07-26 16:14:02 +02:00
Clifford Wolf
97a59851a6
Added RTLIL::Cell::has(portname)
2014-07-26 16:11:28 +02:00
Clifford Wolf
f8fdc47d33
Manual fixes for new cell connections API
2014-07-26 15:58:23 +02:00
Clifford Wolf
b7dda72302
Changed users of cell->connections_ to the new API (sed command)
...
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
2014-07-26 15:58:23 +02:00
Clifford Wolf
cc4f10883b
Renamed RTLIL::{Module,Cell}::connections to connections_
2014-07-26 11:58:03 +02:00
Clifford Wolf
4755e14e7b
Added copy-constructor-like module->addCell(name, other) method
2014-07-26 00:38:44 +02:00
Clifford Wolf
2bec47a404
Use only module->addCell() and module->remove() to create and delete cells
2014-07-25 17:56:19 +02:00
Clifford Wolf
5826670009
Various RTLIL::SigSpec related code cleanups
2014-07-25 14:25:42 +02:00
Clifford Wolf
0520bfea89
Fixed memory corruption in "opt_reduce" pass
2014-07-25 12:49:51 +02:00
Clifford Wolf
c4e4f79a2a
Disabled cover() for non-linux builds
2014-07-25 12:27:36 +02:00
Clifford Wolf
91bf0c90c8
Improvements in "cover" command
2014-07-25 12:04:40 +02:00
Clifford Wolf
6aa792c864
Replaced more old SigChunk programming patterns
2014-07-24 23:10:58 +02:00
Clifford Wolf
9962384d3e
Added cover() calls to opt_const
2014-07-24 20:47:18 +02:00
Clifford Wolf
45b4154b37
Added "make SMALL=1"
2014-07-24 19:03:57 +02:00
Clifford Wolf
b17d6531c8
Added "make PRETTY=1"
2014-07-24 17:15:01 +02:00
Clifford Wolf
2f54345cff
Added "cover" command
2014-07-24 16:14:19 +02:00
Clifford Wolf
20a7965f61
Various small fixes (from gcc compiler warnings)
2014-07-23 20:45:27 +02:00
Clifford Wolf
c094c53de8
Removed RTLIL::SigSpec::optimize()
2014-07-23 20:32:28 +02:00
Clifford Wolf
a62c21c9c6
Removed RTLIL::SigSpec::expand() method
2014-07-23 19:34:51 +02:00
Clifford Wolf
4e802eb7f6
Fixed all users of SigSpec::chunks_rw() and removed it
2014-07-23 15:36:09 +02:00
Clifford Wolf
ec923652e2
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
2014-07-23 09:52:55 +02:00
Clifford Wolf
a8d3a68971
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
2014-07-23 09:49:43 +02:00
Clifford Wolf
260c19ec5a
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3
2014-07-23 09:34:47 +02:00
Clifford Wolf
4a6d234ec7
SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commands
2014-07-22 23:11:36 +02:00
Clifford Wolf
65a939cb27
Fixed memory corruption with new SigSpec API in proc_mux
2014-07-22 22:54:39 +02:00
Clifford Wolf
e7e30f1c86
fixed memory leak in fsm_opt
2014-07-22 22:52:57 +02:00
Clifford Wolf
28b3fd05fa
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
2014-07-22 20:58:44 +02:00
Clifford Wolf
4b4048bc5f
SigSpec refactoring: using the accessor functions everywhere
2014-07-22 20:39:37 +02:00
Clifford Wolf
a233762a81
SigSpec refactoring: renamed chunks and width to __chunks and __width
2014-07-22 20:39:37 +02:00
Clifford Wolf
137dbf3cf7
Added "opt_const -keepdc"
2014-07-21 21:38:55 +02:00
Clifford Wolf
1873480ca5
Added mul to mux conversion to "opt_const -fine"
2014-07-21 17:19:50 +02:00
Clifford Wolf
1241a9fd50
Added "opt_const -fine" and "opt_reduce -fine"
2014-07-21 16:34:16 +02:00
Clifford Wolf
e035f1d886
Added opt_const support for simple identities
2014-07-21 14:41:02 +02:00
Clifford Wolf
361e0d62ff
Replaced depricated NEW_WIRE macro with module->addWire() calls
2014-07-21 12:42:02 +02:00
Clifford Wolf
1d88f1cf9f
Removed deprecated module->new_wire()
2014-07-21 12:35:06 +02:00
Clifford Wolf
3cb61d03f8
Wider range of cell types supported in "share" pass
2014-07-21 12:18:29 +02:00
Clifford Wolf
b49beab1f3
Use ezSAT::non_incremental() in "share" pass
2014-07-21 02:08:38 +02:00
Clifford Wolf
04fcb07213
Added support for resource sharing in mux control logic
2014-07-20 20:44:14 +02:00
Clifford Wolf
1ce5e83555
Added "select -assert-count"
2014-07-20 20:15:49 +02:00
Clifford Wolf
e9506bb2da
Supercell creation for $div/$mod worked all along, fixed test benches
2014-07-20 18:54:06 +02:00
Clifford Wolf
ff28029fdb
Fixed creation of shift supercells in "share" pass
2014-07-20 17:06:36 +02:00
Clifford Wolf
4c38ec1cc8
Added "miter -equiv -flatten"
2014-07-20 15:33:07 +02:00
Clifford Wolf
8d04ca7d22
Added call_on_selection() and call_on_module() API
2014-07-20 15:33:06 +02:00
Clifford Wolf
5b3ee7a072
Added "share" supercell creation
2014-07-20 15:01:17 +02:00
Clifford Wolf
7b98e46ac3
Added removing of always inactive cells to "share" pass
2014-07-20 13:24:36 +02:00
Clifford Wolf
8819493db4
Progress in "share" pass
2014-07-20 11:04:52 +02:00
Clifford Wolf
15fd615da5
Progress in "share" pass
2014-07-20 03:03:04 +02:00
Clifford Wolf
2278995bd8
Started to implement real resource sharing
2014-07-19 20:54:32 +02:00
Clifford Wolf
efd9604dfb
Improved memory_share log messages
2014-07-19 15:46:11 +02:00
Clifford Wolf
e0a819dbe5
More verbose memory_share help message
2014-07-19 15:34:14 +02:00
Clifford Wolf
297a0962ea
Added SAT-based write-port sharing to memory_share
2014-07-19 15:33:55 +02:00
Clifford Wolf
26f982ac0b
Fixed bug in memory_share feedback-to-en code
2014-07-19 15:32:14 +02:00
Clifford Wolf
e441f07d89
Added translation from read-feedback to en-signals in memory_share
2014-07-18 16:46:40 +02:00
Clifford Wolf
44f13aff92
Improved seeding of color rng in show command
2014-07-18 16:44:45 +02:00
Clifford Wolf
a341931972
Only create collision detect logic in memory_share if necessary
2014-07-18 14:32:40 +02:00
Clifford Wolf
ab4b26679f
Added memory_share
2014-07-18 13:16:56 +02:00
Clifford Wolf
309ae98246
Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port
2014-07-18 10:28:45 +02:00
Clifford Wolf
1b00861d0a
Improved opt_reduce handling of mem wr_en mux bits
2014-07-17 12:12:04 +02:00
Clifford Wolf
b76bf05cda
Added support for "blackbox" attribute to iopadmap
2014-07-17 08:59:07 +02:00
Clifford Wolf
64a6906cc4
Added support for "blackbox" attribute to flatten/techmap
2014-07-17 08:58:51 +02:00
Clifford Wolf
d678b6533d
improved opt_reduce for $mem/$memwr WR_EN multiplexers
2014-07-16 14:08:51 +02:00
Clifford Wolf
765f172211
Changes to "memory" pass for new $memwr/$mem WR_EN interface
2014-07-16 12:49:50 +02:00
Clifford Wolf
3b52121d32
now ignore init attributes on non-register wires in sat command
2014-07-05 11:18:38 +02:00
Clifford Wolf
1c85584fe5
Do not create $dffsr cells with no-op resets in proc_dff
2014-06-19 12:29:29 +02:00
Clifford Wolf
22a998903b
Added %D and %c select commands
2014-06-14 16:19:32 +02:00
Clifford Wolf
744e518467
fixed cell array handling of positional arguments
2014-06-07 12:17:11 +02:00
Clifford Wolf
e275e8eef9
Add support for cell arrays
2014-06-07 11:48:50 +02:00
Clifford Wolf
7020f7fc13
added tee cmd
2014-06-03 09:23:31 +02:00
Clifford Wolf
68c99bf734
Fixed log messages in memory_dff
2014-06-01 11:32:27 +02:00
Johann Glaser
278085fa01
added log_header to miter and expose pass, show cell type for exposed ports
2014-05-28 18:05:38 +02:00
Johann Glaser
684c85902d
be more verbose when techmap yielded processes
2014-05-26 17:13:41 +02:00
Clifford Wolf
68c059565a
Fixed bug in opt_reduce (see vloghammer issue_044)
2014-05-12 12:45:47 +02:00
Clifford Wolf
f69b5800c9
fixed syntax error in dot file created by "show" command
2014-05-10 16:22:56 +02:00
Clifford Wolf
9a34486bfb
Fixed performance problem in opt_mux with nets driven by many conflicting drivers
2014-03-19 10:05:01 +01:00
Clifford Wolf
34e54cda5b
Small improvement in SAT log messages
2014-03-13 13:12:49 +01:00
Clifford Wolf
fad8558eb5
Merged OSX fixes from Siesh1oo with some modifications
2014-03-13 12:48:10 +01:00
Siesh1oo
8127d5e8c3
- kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname().
...
This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems.
- passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
2014-03-12 23:17:14 +01:00
Clifford Wolf
9087ece97c
OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/yosys
...
(see https://github.com/cliffordwolf/yosys/pull/28 )
2014-03-11 14:52:37 +01:00
Clifford Wolf
91704a7853
Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
...
(see https://github.com/cliffordwolf/yosys/pull/28 )
2014-03-11 14:24:24 +01:00
Clifford Wolf
fa75c8286e
Fixed memory corruption in passes/abc/blifparse.cc
2014-03-11 13:09:01 +01:00
Clifford Wolf
fcae92868d
Fixed dumping of timing() { .. } block in libparse
2014-03-09 15:16:07 +01:00
Clifford Wolf
22aabe05c9
Verbose reading of liberty and constr files in ABC pass
2014-03-09 15:15:38 +01:00
Clifford Wolf
e3b11ea2d6
Fixed bug in freduce command
2014-03-07 18:44:23 +01:00
Clifford Wolf
6f8865d81a
Some minor code cleanups in freduce command
2014-03-07 18:29:04 +01:00
Clifford Wolf
54d74cf616
Added freduce -dump
2014-03-06 22:06:58 +01:00
Clifford Wolf
da5859a674
Added freduce -stop
2014-03-06 18:14:26 +01:00
Clifford Wolf
9b9c3327cc
Fixed undef handling in opt_reduce
2014-03-06 14:18:34 +01:00
Clifford Wolf
1ecaf1bb76
Added techmap -max_iter option
2014-03-06 12:15:17 +01:00
Clifford Wolf
96e753041d
fixed freduce for Minisat::SimpSolver: use frozen_literal()
2014-03-03 02:14:27 +01:00
Clifford Wolf
9e99984336
Fixed const folding of $bu0 cells
2014-02-27 04:09:32 +01:00
Clifford Wolf
548519875b
Fixed bug (typo) in passes/opt/opt_const.cc
2014-02-22 17:07:22 +01:00
Clifford Wolf
8b508dc90b
Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst
2014-02-21 23:34:45 +01:00
Clifford Wolf
4e43cb7317
Added _TECHMAP_REPLACE_ feature to techmap
2014-02-20 23:42:07 +01:00
Clifford Wolf
737b71c735
Added "extract -ignore_parameters" and "extract -ignore_param ..."
2014-02-20 23:31:13 +01:00
Clifford Wolf
236fc4209c
Added "extract -map %<design_name>"
2014-02-20 23:30:15 +01:00
Clifford Wolf
483c99fe46
Added "design -push" and "design -pop"
2014-02-20 23:28:59 +01:00
Clifford Wolf
0dadfed46d
Added connwrappers command
2014-02-20 20:44:11 +01:00
Clifford Wolf
23a3b488a0
Merge branch 'master' of github.com:cliffordwolf/yosys
2014-02-18 20:05:53 +01:00
Clifford Wolf
a71d09421d
Added techmap support for _TECHMAP_CONNMAP_*_
2014-02-18 19:51:00 +01:00
Clifford Wolf
a78bba1f5c
Added "sat -dump_cnf"
2014-02-18 09:29:08 +01:00
Clifford Wolf
32af10fa9b
Coding style corrections in SatHelper::dump_model_to_vcd()
2014-02-18 09:28:05 +01:00
Clifford Wolf
13051e6acf
Added "sat -initsteps"
2014-02-18 09:03:16 +01:00
Clifford Wolf
0851c2b6ea
Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanups
2014-02-17 13:59:39 +01:00
Andrew Zonenberg
4a948d780a
Added "-dump_fail_to_vcd" argument to SAT solver
2014-02-17 13:52:36 +01:00
Clifford Wolf
ca53ef5098
Better preserve wires when flattening (in comparison to techmap)
2014-02-17 09:44:39 +01:00
Clifford Wolf
6d63f39eb6
Added some additional checks to techmap
2014-02-16 22:18:06 +01:00
Clifford Wolf
a9b11d7c83
Added CONSTMSK and CONSTVAL feature to techmap
2014-02-16 21:58:59 +01:00
Clifford Wolf
28e14ee50a
Fixed handling of "keep" attribute on wires in opt_clean
2014-02-16 21:58:27 +01:00
Clifford Wolf
42ce3db983
Fixed use of selection in splitnets command
2014-02-16 17:39:50 +01:00
Clifford Wolf
d3dc22a90f
Added recursion support to techmap
2014-02-16 17:16:44 +01:00
Clifford Wolf
9a816b65a8
Added != support for relational select pattern
2014-02-16 00:16:54 +01:00
Clifford Wolf
623a68f528
Added iopadmap -bits
2014-02-15 21:59:26 +01:00
Clifford Wolf
cdf0f10760
Fixed dfflibmap for cell libraries with no set-reset-ff
2014-02-15 16:34:12 +01:00
Clifford Wolf
67effc9f5b
Fixed opt_const handling of double invert with non-1 output width
2014-02-15 13:16:08 +01:00
Clifford Wolf
3121d19d95
Added abc -keepff option
2014-02-14 11:28:42 +01:00
Clifford Wolf
de3ea9269a
updated default ABC command strings
2014-02-13 19:14:15 +01:00
Clifford Wolf
a123941618
Updated ABC
2014-02-13 18:56:36 +01:00
Clifford Wolf
cd9e8741a7
Implemented read_verilog -defer
2014-02-13 13:59:13 +01:00
Clifford Wolf
b463907890
Removed double blanks in ABC default command sequences
2014-02-13 08:12:52 +01:00
Clifford Wolf
7664f5d92b
Updated ABC and some related changes
2014-02-13 08:07:08 +01:00
Clifford Wolf
ab71bd0746
Updated ABC to rev e97a6e1d59b9
2014-02-12 08:35:42 +01:00
Clifford Wolf
38469e7686
Various improvements in expose command (added -sep and -cut)
2014-02-09 11:07:46 +01:00
Clifford Wolf
b6f33576d5
Added delete {-input|-output|-port}
2014-02-09 10:03:26 +01:00
Clifford Wolf
b3b5fac191
Bugfix in delete command
2014-02-09 09:34:58 +01:00
Clifford Wolf
85914c36e5
Fixed handling of async reset in expose -evert-dff
2014-02-08 21:26:40 +01:00
Clifford Wolf
db86aaa07d
Build fixes for log cmd
2014-02-08 21:21:51 +01:00
Clifford Wolf
c06de50f05
Merge branch 'master' of github.com:cliffordwolf/yosys
2014-02-08 21:08:46 +01:00
Clifford Wolf
0935e20003
Implemented expose -evert-dff
2014-02-08 21:08:38 +01:00
Johann Glaser
af14bb5f65
added "log" command
2014-02-08 19:19:32 +01:00
Clifford Wolf
7f52c18a22
Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect
2014-02-08 19:13:19 +01:00
Clifford Wolf
926fa61119
Added various new options to splice command
2014-02-08 16:37:18 +01:00
Clifford Wolf
0c11d04144
Added %a select operator
2014-02-08 16:31:38 +01:00
Clifford Wolf
6644f80d97
Moved some passes to other source directories
2014-02-08 14:39:15 +01:00
Clifford Wolf
03ee63ff80
Added support for "keep" attribute to abc pass
2014-02-08 14:25:29 +01:00
Clifford Wolf
82c98bbbe6
Added opt -purge (frontend to opt_clean -purge)
2014-02-08 14:21:34 +01:00