Marcelina Kościelnicka
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0a8eaca322
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nexus: Use `memory_libmap` pass.
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2022-05-18 17:32:56 +02:00 |
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Marcelina Kościelnicka
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958c3a46ad
|
nexus: Fix arith_map CO signal.
Fixes #3187.
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2022-02-06 13:05:30 +01:00 |
gatecat
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f699c4ba58
|
nexus: Fix BB sim model
Signed-off-by: gatecat <gatecat@ds0.me>
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2022-01-19 18:14:24 +00:00 |
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Marcelina Kościelnicka
|
15b0d717ed
|
iopadmap: Add native support for negative-polarity output enable.
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2021-11-09 15:40:16 +01:00 |
Pepijn de Vos
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c2d358484f
|
Gowin: deal with active-low tristate (#2971)
* deal with active-low tristate
* remove empty port
* update sim models
* add expected lut1 to tests
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2021-08-20 21:21:06 +02:00 |
Claire Xenia Wolf
|
0ada13cbe2
|
Use HTTPS for website links, gatecat email
git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
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2021-06-09 12:16:56 +02:00 |
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Claire Xenia Wolf
|
72787f52fc
|
Fixing old e-mail addresses and deadnames
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
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2021-06-08 00:39:36 +02:00 |
|
gatecat
|
cae905f551
|
Blackbox all whiteboxes after synthesis
This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.
Signed-off-by: gatecat <gatecat@ds0.me>
|
2021-03-17 21:07:20 +00:00 |
David Shah
|
f5cc1224f9
|
nexus: Add MULTADDSUB9X9WIDE sim model
Signed-off-by: David Shah <dave@ds0.me>
|
2020-12-08 15:49:20 +00:00 |
|
David Shah
|
17812a1560
|
nexus: Add LRAM inference
Signed-off-by: David Shah <dave@ds0.me>
|
2020-12-07 13:27:17 +00:00 |
|
David Shah
|
264e924abb
|
nexus: More efficient CO mapping
Signed-off-by: David Shah <dave@ds0.me>
|
2020-12-02 17:08:39 +00:00 |
|
David Shah
|
9f241c9a42
|
nexus: DSP inference support
Signed-off-by: David Shah <dave@ds0.me>
|
2020-11-20 08:45:55 +00:00 |
|
David Shah
|
923843b3fa
|
nexus: Add DSP simulation model
Signed-off-by: David Shah <dave@ds0.me>
|
2020-11-18 10:21:17 +00:00 |
|
David Shah
|
6d63e58e46
|
nexus: Add make_transp to BRAMs
Signed-off-by: David Shah <dave@ds0.me>
|
2020-10-22 15:11:59 +01:00 |
|
David Shah
|
4d584d9319
|
synth_nexus: Initial implementation
Signed-off-by: David Shah <dave@ds0.me>
|
2020-10-15 08:52:15 +01:00 |