320 Commits

Author	SHA1	Message	Date
Clifford Wolf	223892ac28	Improved user-friendliness of "sat" and "eval" expression parsing	2013-11-09 12:02:27 +01:00
Clifford Wolf	947bd9b96b	Renamed extend_un0() to extend_u0() and use it in genrtlil	2013-11-07 18:17:10 +01:00
Clifford Wolf	0e1661f84e	Fixed type of sign extension in opt_const $eq/$ne handling	2013-11-07 16:53:28 +01:00
Clifford Wolf	bd2c8ec886	Added design->full_selection() helper method	2013-10-27 09:30:58 +01:00
Clifford Wolf	e679a5d046	Fixed handling of boolean attributes (passes)	2013-10-24 11:37:54 +02:00
Clifford Wolf	eae43e2db4	Fixed handling of boolean attributes (kernel)	2013-10-24 10:59:27 +02:00
Clifford Wolf	8e8f1994b8	Changed NEW_WIRE API to return the wire, not the signal	2013-10-18 14:19:45 +02:00
Clifford Wolf	cc5e379eca	Added RTLIL NEW_WIRE macro	2013-10-18 13:25:24 +02:00
Clifford Wolf	376150c926	Added techmap -opt mode	2013-08-09 15:20:22 +02:00
Clifford Wolf	05483619f0	Some fixes to improve determinism	2013-08-09 12:42:32 +02:00
Clifford Wolf	0f38008ed3	Added "design" command (-reset, -save, -load)	2013-07-27 14:27:51 +02:00
Clifford Wolf	21e38bed98	Added "eval" pass	2013-06-19 09:30:37 +02:00
Clifford Wolf	a046a302f0	Fixed build with clang	2013-06-18 19:54:33 +02:00
Clifford Wolf	6971c4db62	Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API	2013-06-18 17:11:13 +02:00
Clifford Wolf	21d9251e52	Added "dump" command (part ilang backend)	2013-06-02 17:53:30 +02:00
Clifford Wolf	88af5b6a16	Improved opt_share for reduce cells	2013-03-29 11:19:21 +01:00
Clifford Wolf	d4680fd5a0	Added design->select() api and use it in extract pass	2013-03-03 20:53:24 +01:00
Clifford Wolf	1bc0f04789	Added id2cstr API	2013-03-01 09:01:49 +01:00
Clifford Wolf	51c2b797b3	Do not unescape identifiers starting with \$	2013-03-01 01:10:11 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00