Clifford Wolf
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2541489105
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Added techmap CONSTMAP feature
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2014-07-30 22:04:30 +02:00 |
Clifford Wolf
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6c05badc43
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New techmap default rules for $shr $sshr $shl $sshl
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2014-07-30 18:49:12 +02:00 |
Clifford Wolf
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2145e57ef0
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Bugfix in simlib.v for iverilog
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2014-07-29 19:23:31 +02:00 |
Clifford Wolf
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397b00252d
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Added $shift and $shiftx cell types (needed for correct part select behavior)
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2014-07-29 16:35:13 +02:00 |
Clifford Wolf
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b17d6531c8
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Added "make PRETTY=1"
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2014-07-24 17:15:01 +02:00 |
Clifford Wolf
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f1ca93a0a3
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Fixed simlib.v model for $mem
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2014-07-17 16:48:36 +02:00 |
Clifford Wolf
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dcdd5c11b4
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Updated simlib to new $mem/$memwr interface
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2014-07-16 11:46:40 +02:00 |
Clifford Wolf
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7370ae01e9
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Added SIMLIB_NOLUT to simlib.v
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2014-04-02 21:28:33 +02:00 |
Clifford Wolf
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e24797add0
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Added SIMLIB_NOSR to simlib.v
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2014-04-02 21:06:55 +02:00 |
Clifford Wolf
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d4a1b0af5b
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Added support for dlatchsr cells
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2014-03-31 14:14:40 +02:00 |
Clifford Wolf
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7aa2d746b7
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Merged addition of SED makefile variable from github.com/Siesh1oo/yosys
(see https://github.com/cliffordwolf/yosys/pull/28)
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2014-03-11 14:42:58 +01:00 |
Clifford Wolf
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973507d85b
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Fixes for improved techmap of shifts with large B inputs
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2014-03-06 13:33:12 +01:00 |
Clifford Wolf
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8406e7f7b6
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Strictly zero-extend unsigned A-inputs of shift operations in techmap
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2014-03-06 12:15:44 +01:00 |
Clifford Wolf
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d7f29bb23f
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Improved techmap of shift with wide B inputs
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2014-03-06 12:14:20 +01:00 |
Clifford Wolf
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fc3b3c4ec3
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Added $slice and $concat cell types
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2014-02-07 17:44:57 +01:00 |
Clifford Wolf
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a6750b3753
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Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
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2014-02-03 13:01:45 +01:00 |
Clifford Wolf
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ed8ad99960
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More changes to techlibs/common/simlib.v for LEC
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2014-01-31 11:21:29 +01:00 |
Clifford Wolf
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a86f33653d
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Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)
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2014-01-29 00:36:03 +01:00 |
Clifford Wolf
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1e67099b77
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Added $assert cell
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2014-01-19 14:03:40 +01:00 |
Clifford Wolf
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3d7a1491aa
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Fixed $lut simlib model for a wider range of tools
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2014-01-18 19:31:40 +01:00 |
Clifford Wolf
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2fbaaaca7a
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More changes to simlib to make it friendlier to a wider range of tools
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2014-01-18 19:13:43 +01:00 |
Clifford Wolf
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4a9e133fab
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Fixed a type in $mem model in simlib.v
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2014-01-18 18:54:50 +01:00 |
Clifford Wolf
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bef17eeb10
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Removed cases of trailing comma in stdcells.v
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2014-01-18 15:36:17 +01:00 |
Clifford Wolf
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5b96675696
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Added $bu0 cell to simlib.v
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2014-01-18 15:35:15 +01:00 |
Clifford Wolf
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db9cf544b8
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Added techlibs/common/pmux2mux.v
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2014-01-17 20:06:15 +01:00 |
Clifford Wolf
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b3b00f1bf4
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Various small cleanups in stdcells.v techmap code
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2013-12-31 15:41:40 +01:00 |
Clifford Wolf
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c69c416d28
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Added $bu0 cell (for easy correct $eq/$ne mapping)
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2013-12-28 12:02:14 +01:00 |
Clifford Wolf
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369bf81a70
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Added support for non-const === and !== (for miter circuits)
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2013-12-27 14:20:15 +01:00 |
Clifford Wolf
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76f7c10cfc
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Using simplemap mappers from techmap
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2013-11-24 23:31:14 +01:00 |
Clifford Wolf
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1afe6589df
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Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
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2013-11-24 20:44:00 +01:00 |
Clifford Wolf
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0c91f890c9
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Install simlib in datdir
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2013-11-19 23:05:46 +01:00 |
Clifford Wolf
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e5b974fa2a
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Cleanups and bugfixes in response to new internal cell checker
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2013-11-11 00:39:45 +01:00 |
Clifford Wolf
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404b46674b
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Fixed techmap of $reduce_xnor with multi-bit outputs
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2013-11-07 00:58:06 +01:00 |
Clifford Wolf
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b41740060b
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Fixed techmap of $gt and $ge with multi-bit outputs
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2013-11-06 22:59:45 +01:00 |
Clifford Wolf
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6fcbc79b5c
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Improved width extension with regard to undef propagation
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2013-11-06 21:05:11 +01:00 |
Clifford Wolf
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0836a1f2ba
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Bugfix in dffsr techmap rules
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2013-10-18 13:24:44 +02:00 |
Clifford Wolf
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8197169f8d
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Added techmap rules for $sr, $dffsr and $dlatch
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2013-10-18 12:29:21 +02:00 |
Clifford Wolf
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e0f693cbb0
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Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_
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2013-10-18 12:13:34 +02:00 |
Clifford Wolf
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5998c101a4
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Added $sr, $dffsr and $dlatch cell types
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2013-10-18 11:56:16 +02:00 |
Clifford Wolf
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288ba9618a
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Moved common techlib files to techlibs/common
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2013-09-15 11:52:57 +02:00 |