riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
5,299 Commits 81 Branches 48 Tags 64 MiB
Commit Graph

59 Commits

Author SHA1 Message Date
Eddie Hung 7685469ee2 Add default entry to testcase 2019-04-11 15:03:40 -07:00
Jim Lawson 71bcc4c644 Address requested changes - don't require non-$ name. 
Suppress warning if name does begin with a `$`.
Fix hierachy tests so they have something to grep.
Announce hierarchy test types.
 2019-02-22 16:06:10 -08:00
Jim Lawson 5c4a72c43e Fix normal (non-array) hierarchy -auto-top. 
Add simple test.
 2019-02-19 14:35:15 -08:00
Udi Finkelstein 73d426bc87 Modified errors into warnings 
No longer false warnings for memories and assertions
 2018-06-05 18:03:22 +03:00
Udi Finkelstein 80d9d15f1c reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files 2018-06-05 18:00:06 +03:00
Clifford Wolf 724cead61d Added "pmuxtree" command 2015-04-07 20:27:10 +02:00
Clifford Wolf 01ef34c147 Added tests/various/constmsk_test.ys 2014-09-04 15:07:30 +02:00
Clifford Wolf d49dec1f86 Added tests/various/.gitignore 2014-07-26 17:43:41 +02:00
Clifford Wolf b21ebe1859 Added tests/various/submod_extract.ys 2014-07-26 17:22:18 +02:00