riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
158 Commits 89 Branches 51 Tags 35 MiB
Commit Graph

2 Commits

Author SHA1 Message Date
Clifford Wolf 041c06bd9d Create nice errors when calling RTLIL::Module::derive() of base class 2013-03-26 19:27:49 +01:00
Clifford Wolf 7764d0ba1d initial import 2013-01-05 11:13:26 +01:00