riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
5,132 Commits 92 Branches 49 Tags 38 MiB
Commit Graph

5132 Commits

Author SHA1 Message Date
Eddie Hung f9fb05cf66 synth_xilinx to use shregmap with -minlen 3 2019-03-25 13:18:55 -07:00
Eddie Hung 6b90d3cf6c Merge remote-tracking branch 'origin/master' into xc7srl 2019-03-25 13:17:22 -07:00
Clifford Wolf ddc1a4488e Add "cutpoint" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-25 19:49:00 +01:00
Eddie Hung b7a3d35c6b Create one $shiftx per bit in width 2019-03-25 11:16:56 -07:00
Clifford Wolf 9ec50ca7b9
Merge pull request #896 from YosysHQ/transp_fixes 
memory_bram: Fix multiclock make_transp
 2019-03-25 14:55:16 +01:00
Clifford Wolf 2bb9632944
Merge pull request #897 from trcwm/libertyfixes 
Liberty parser: Accept ranges [A:B], and ignore missing ';'.
 2019-03-25 14:47:33 +01:00
Niels Moseley 1f7f54e68e spaces -> tabs 2019-03-25 14:12:04 +01:00
Niels Moseley 9d9cc8a314 EOL is now accepted as ';' replacement on lines that look like: feature_xyz(option) 2019-03-25 12:15:10 +01:00
Niels Moseley 3b3b77291a Updated the liberty parser to accept [A:B] ranges (AST has not been updated). Liberty parser now also accepts key : value pair lines that do not end in ';'. 2019-03-24 22:54:18 +01:00
David Shah ac6cc88db3 memory_bram: Fix multiclock make_transp 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-24 16:21:36 +00:00
Eddie Hung 2507d01b03 Add a pmux-to-shiftx optimisation to proc_mux 2019-03-23 16:45:36 -07:00
Eddie Hung bf83c074c8 Cope with SHREG not having E port; Revert $pmux fine tune 2019-03-23 16:09:38 -07:00
Clifford Wolf ccfa2fe01c Add "mutate -none -mode", "mutate -mode none" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-23 20:20:32 +01:00
Clifford Wolf 59c44bb61a Add "mutate -s <filename>" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-23 17:53:09 +01:00
Clifford Wolf 2cf71e2a7b
Merge pull request #893 from YosysHQ/clifford/btormeminit 
Memory init support in write_btor
 2019-03-23 16:02:01 +01:00
Clifford Wolf 1eff8be8f0 Add support for memory initialization to write_btor 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-23 14:40:01 +01:00
Clifford Wolf e78f5a3055 Fix BTOR output tags syntax in writye_btor 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-23 14:39:42 +01:00
Clifford Wolf 3b796c033c Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-23 14:38:48 +01:00
Eddie Hung 098bd5758f Add support for SHREGMAP+$mux, also fine tune $pmux 2019-03-22 23:22:19 -07:00
Eddie Hung 0895093c7c Leftover printf 2019-03-22 19:14:04 -07:00
Eddie Hung 456295eb66 Fixes for multibit 2019-03-22 18:32:42 -07:00
Eddie Hung 03d108cd1f Working for 1 bit 2019-03-22 17:46:49 -07:00
Eddie Hung 46753cf89f Merge remote-tracking branch 'origin/master' into xc7srl 2019-03-22 13:10:42 -07:00
Clifford Wolf a440f82586
Merge pull request #889 from YosysHQ/clifford/fix888 
Fix mem2reg handling of memories with upto data ports
 2019-03-22 18:03:06 +01:00
Clifford Wolf 7d8d0d0155
Merge pull request #890 from YosysHQ/clifford/fix887 
Trim init attributes when resizing FFs in "wreduce"
 2019-03-22 18:02:29 +01:00
David Shah 7a6551de36
Merge pull request #891 from YosysHQ/xilinx_keep 
xilinx: Add keep attribute where appropriate
 2019-03-22 14:28:29 +00:00
David Shah 46f6a60d58 xilinx: Add keep attribute where appropriate 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 13:57:17 +00:00
Clifford Wolf 7cfd83c341 Trim init attributes when resizing FFs in "wreduce", fixes #887 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-22 11:42:19 +01:00
Eddie Hung 4cc6b3e942 Add '-nosrl' option to synth_xilinx 2019-03-21 15:04:44 -07:00
Clifford Wolf 638be461c3 Fix mem2reg handling of memories with upto data ports, fixes #888 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-21 22:21:17 +01:00
Clifford Wolf da42f10765 Improve "read_verilog -dump_vlog[12]" handling of upto ranges 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-21 22:20:16 +01:00
Clifford Wolf 9b0e7af6d7 Improve read_verilog debug output capabilities 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-21 20:52:29 +01:00
Eddie Hung 5597270b9e Opt 2019-03-21 10:20:27 -07:00
Eddie Hung 2b911e270b Fix spacing 2019-03-20 12:28:39 -07:00
Eddie Hung 81c207fb9b Fine tune cells_map.v 2019-03-20 10:55:14 -07:00
Eddie Hung 505e4c2d59 Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length 2019-03-19 21:58:05 -07:00
Eddie Hung 5445cd4d00 Add support for variable length Xilinx SRL > 128 2019-03-19 17:44:33 -07:00
Eddie Hung ae2a625d05 Restore original synth_xilinx commands 2019-03-19 16:14:08 -07:00
Eddie Hung 9156e18f92 Fix spacing 2019-03-19 16:12:32 -07:00
Eddie Hung 4cd8f02973 shregmap -tech xilinx to delete $shiftx for var length SRL 2019-03-19 15:05:08 -07:00
Eddie Hung f239cb821e Fix INIT for variable length SRs that have been bumped up one 2019-03-19 14:54:43 -07:00
Eddie Hung 24553326dd Merge remote-tracking branch 'origin/master' into xc7srl 2019-03-19 13:11:30 -07:00
Eddie Hung 0ea7eba5f1 Make output port a non chain user 2019-03-19 13:08:43 -07:00
Clifford Wolf 8c0740bcf7
Merge pull request #885 from YosysHQ/clifford/fix873 
Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873
 2019-03-19 20:31:53 +01:00
Clifford Wolf fe1fb1336b Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-19 20:30:28 +01:00
Eddie Hung a7ac8393d4
Merge pull request #808 from eddiehung/read_aiger 
Add new read_aiger frontend
 2019-03-19 09:41:40 -07:00
Eddie Hung 02e8dc7ad2 Merge https://github.com/YosysHQ/yosys into read_aiger 2019-03-19 08:52:31 -07:00
Eddie Hung 3e89cf68bd Add author name 2019-03-19 08:52:06 -07:00
Clifford Wolf 61f37706f9
Merge pull request #884 from zachjs/master 
fix local name resolution in prefix constructs
 2019-03-19 14:08:57 +01:00
Zachary Snow a5f4b83637 fix local name resolution in prefix constructs 2019-03-18 20:43:20 -04:00