Diego
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f9272fc56d
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GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow
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2019-04-12 23:40:02 -05:00 |
Eddie Hung
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fecafb2207
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Forgot backslashes
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2019-04-12 18:22:44 -07:00 |
Eddie Hung
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9bfcd80063
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Handle __dummy_o__ and __const[01]__ in read_aiger not abc
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2019-04-12 18:21:16 -07:00 |
Eddie Hung
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482a60825b
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abc to ignore __dummy_o__ and __const[01]__ when re-integrating
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2019-04-12 18:16:50 -07:00 |
Eddie Hung
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fe0b421212
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Output __const0__ and __const1__ CIs
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2019-04-12 18:16:25 -07:00 |
Eddie Hung
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c776db3320
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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
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2019-04-12 17:09:24 -07:00 |
Eddie Hung
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acf3f5694b
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Fix inout handling for -map option
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2019-04-12 17:02:24 -07:00 |
Eddie Hung
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a16123cc7d
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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
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2019-04-12 16:31:12 -07:00 |
Eddie Hung
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d880f73c79
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Merge remote-tracking branch 'origin/master' into xaig
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2019-04-12 16:30:53 -07:00 |
Eddie Hung
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88d43a519b
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Use -map instead of -symbols for aiger
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2019-04-12 16:29:14 -07:00 |
Eddie Hung
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686e772f0b
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ci_bits and co_bits now a list, order is important for ABC
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2019-04-12 16:17:48 -07:00 |
Eddie Hung
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ada130b459
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Also cope with duplicated CIs
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2019-04-12 16:17:12 -07:00 |
Eddie Hung
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c748391730
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WIP
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2019-04-12 14:13:11 -07:00 |
Eddie Hung
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941365b4bb
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Comment out
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2019-04-12 12:29:04 -07:00 |
Eddie Hung
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04e466d5e4
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Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
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2019-04-12 12:28:37 -07:00 |
Eddie Hung
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1c6f0cffd9
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Cope with an output having same name as an input (i.e. CO)
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2019-04-12 12:27:07 -07:00 |
Eddie Hung
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f77da46a87
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Merge remote-tracking branch 'origin/master' into xaig
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2019-04-12 12:21:48 -07:00 |
Eddie Hung
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db1a5ec6a2
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Merge pull request #928 from litghost/add_xc7_sim_models
Add additional cells sim models for core 7-series primitives.
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2019-04-12 11:52:45 -07:00 |
Eddie Hung
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ca8ef92a82
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PI before CI
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2019-04-12 10:36:05 -07:00 |
Eddie Hung
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8228b593ef
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Merge remote-tracking branch 'origin/master' into xc7mux
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2019-04-12 09:46:07 -07:00 |
Keith Rothman
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1f9235ede5
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Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-04-12 09:35:15 -07:00 |
Clifford Wolf
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9d6586b4e1
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Merge pull request #933 from dh73/master
Fixing issues in CycloneV cell sim
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2019-04-12 14:57:36 +02:00 |
Clifford Wolf
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48bc203653
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Merge pull request #932 from YosysHQ/eddie/fixdlatch
Recognise default entry in case even if all cases covered (fix for #931)
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2019-04-12 14:57:01 +02:00 |
Diego
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643ae9bfc5
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Fixing issues in CycloneV cell sim
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2019-04-11 19:59:03 -05:00 |
Eddie Hung
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3c1f1a6605
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Fix ordering of when to insert zero index
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2019-04-11 16:25:59 -07:00 |
Eddie Hung
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53513c52df
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Merge remote-tracking branch 'origin/pmux2shiftx' into xc7mux
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2019-04-11 16:21:01 -07:00 |
Eddie Hung
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f587950bde
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More unused
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2019-04-11 16:20:43 -07:00 |
Eddie Hung
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35181a7866
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Merge remote-tracking branch 'origin/pmux2shiftx' into xc7mux
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2019-04-11 16:18:45 -07:00 |
Eddie Hung
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b15b410b41
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Remove unused
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2019-04-11 16:18:01 -07:00 |
Eddie Hung
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b1f1db2fcf
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Fixes
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2019-04-11 16:17:09 -07:00 |
Eddie Hung
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e8c26f2839
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WIP
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2019-04-11 15:52:04 -07:00 |
Eddie Hung
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09e7eb7aed
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Spelling fixes
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2019-04-11 15:09:13 -07:00 |
Eddie Hung
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7685469ee2
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Add default entry to testcase
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2019-04-11 15:03:40 -07:00 |
Eddie Hung
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adc6efb584
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Recognise default entry in case even if all cases covered (#931)
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2019-04-11 12:34:51 -07:00 |
Eddie Hung
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233edf00fe
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Fix cells_map.v some more
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2019-04-11 10:48:14 -07:00 |
Eddie Hung
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8658b56a08
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More fine tuning
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2019-04-11 10:08:05 -07:00 |
Eddie Hung
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0ec8564099
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Fix cells_map.v
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2019-04-11 10:04:58 -07:00 |
Eddie Hung
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bca3779657
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Fix typo
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2019-04-11 09:25:19 -07:00 |
Eddie Hung
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87b8d29a90
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Juggle opt calls in synth_xilinx
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2019-04-11 09:13:39 -07:00 |
Eddie Hung
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227cc54c16
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Merge branch 'xaig' into xc7mux
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2019-04-10 18:07:11 -07:00 |
Eddie Hung
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2217d59e29
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Add non-input bits driven by unrecognised cells as ci_bits
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2019-04-10 18:06:33 -07:00 |
Eddie Hung
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cd7b2de27f
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WIP for cells_map.v -- maybe working?
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2019-04-10 18:05:09 -07:00 |
Eddie Hung
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3d577586fd
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Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1
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2019-04-10 16:15:23 -07:00 |
Eddie Hung
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3f5dab0d09
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Fix for when B_SIGNED = 1
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2019-04-10 14:51:10 -07:00 |
Eddie Hung
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32561332b2
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Update doc for synth_xilinx
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2019-04-10 14:48:58 -07:00 |
Eddie Hung
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bf92218e0f
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Merge branch 'xaig' into xc7mux
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2019-04-10 14:03:09 -07:00 |
Eddie Hung
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1a49cf29d8
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parse_aiger() to rename all $lut cells after "clean"
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2019-04-10 14:02:23 -07:00 |
Eddie Hung
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17a02df05c
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ff_map.v after abc
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2019-04-10 12:36:06 -07:00 |
Eddie Hung
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1ec949d5ed
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Tidy up
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2019-04-10 09:02:42 -07:00 |
Eddie Hung
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526aef9c2a
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Move map_cells to before map_luts
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2019-04-10 08:50:31 -07:00 |