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4617 Commits

Author SHA1 Message Date
Clifford Wolf e9b34ad5c0 Merge branch 'master' of github.com:YosysHQ/yosys 2019-03-07 22:44:50 -08:00
Clifford Wolf a330c68363 Fix handling of task output ports in clocked always blocks, fixes #857 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 22:44:37 -08:00
Sylvain Munaut 5b6f591033 ice40: Run ice40_braminit pass by default 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-03-08 00:15:46 +01:00
Sylvain Munaut e71055cfe8 ice40: Add ice40_braminit pass to allow initialization of BRAM from file 
This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will
initialize content from a hex file. Same behavior is imlemented in the
simulation model and in a new pass for actual synthesis

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-03-08 00:15:46 +01:00
Clifford Wolf df0598f455
Merge pull request #856 from kprasadvnsi/master 
examples/anlogic/ now also output the SVF file.
 2019-03-07 11:34:12 -08:00
Clifford Wolf 5dfc7becca Use SVA label in smt export if available 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 11:31:46 -08:00
Clifford Wolf 22ff60850e Add support for SVA labels in read_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 11:17:32 -08:00
Clifford Wolf cda37830b0 Add hack for handling SVA labels via Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 10:52:44 -08:00
Clifford Wolf 350dfd3745 Add link to SF2 / igloo2 macro library guide 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 09:08:26 -08:00
Clifford Wolf 8b0719d1e3 Improvements in sf2 cells_sim.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-06 16:18:49 -08:00
Clifford Wolf 2d2c1617ee Add sf2 techmap rules for more FF types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-06 15:47:54 -08:00
Clifford Wolf 78762316aa Refactor SF2 iobuf insertion, Add clkint insertion 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-06 00:41:02 -08:00
Clifford Wolf b1b9edf5cc Improve igloo2 example 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-05 20:47:07 -08:00
Clifford Wolf e22afeae90 Improve igloo2 example 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-05 20:36:00 -08:00
Clifford Wolf da5181a3df Improvements in SF2 flow and demo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-05 20:36:00 -08:00
Kali Prasad 7c03b0b082 examples/anlogic/ now also output the SVF file. 2019-03-06 09:51:11 +05:30
Eddie Hung d03780c3f4
Fix spelling in pmgen/README.md 2019-03-05 17:55:29 -08:00
Clifford Wolf 24d1b92eda Improve igloo2 exmaple 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-05 17:27:58 -08:00
Clifford Wolf bfcd46dbd3
Merge pull request #842 from litghost/merge_upstream 
Changes required for VPR place and route in synth_xilinx
 2019-03-05 15:33:19 -08:00
Clifford Wolf 724576a4e2
Merge pull request #850 from daveshah1/ecp5_warn_conflict 
ecp5: Demote conflicting FF init values to a warning
 2019-03-05 15:23:01 -08:00
Clifford Wolf 3ef427f4a9 Add missing newline 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-05 15:21:04 -08:00
Clifford Wolf ba0da6371e
Merge pull request #851 from kprasadvnsi/master 
Added examples/anlogic/
 2019-03-05 15:20:03 -08:00
Clifford Wolf 855b9dc606
Merge pull request #852 from ucb-bar/firrtlfixes 
Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails
 2019-03-05 15:19:28 -08:00
Clifford Wolf 13844c7658 Use "write_edif -pvector bra" for Xilinx EDIF files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-05 15:16:13 -08:00
Jim Lawson d6c4dfb902 Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails 
Mark dff_init.v as expected to fail since it uses "initial value".
 2019-03-04 13:37:23 -08:00
Kali Prasad 32a901ddf2 Added examples/anlogic/ 2019-03-04 23:26:56 +05:30
Keith Rothman 228f132ec3 Revert BRAM WRITE_MODE changes. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-04 09:22:22 -08:00
David Shah 777864d02e ecp5: Demote conflicting FF init values to a warning 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-04 11:26:20 +00:00
Clifford Wolf 107d884804 Improve igloo2 example 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-03 23:54:35 -08:00
Clifford Wolf a176ac95de Update igloo2 example to Libero v12.0 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-03 21:36:03 -08:00
Clifford Wolf 52f80718a7
Merge pull request #848 from YosysHQ/clifford/fix763 
Fix error for wire decl in always block, fixes 763
 2019-03-02 16:32:58 -08:00
Clifford Wolf dddf837f69
Merge pull request #849 from YosysHQ/clifford/dynports 
Only run derive on blackbox modules when ports have dynamic size
 2019-03-02 16:01:31 -08:00
Clifford Wolf ae9286386d Only run derive on blackbox modules when ports have dynamic size 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 12:36:46 -08:00
Clifford Wolf 3a51714451 Fix error for wire decl in always block, fixes #763 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 11:56:44 -08:00
Clifford Wolf ce6695e22c Fix $global_clock handling vs autowire 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 10:38:13 -08:00
Clifford Wolf 65412466c5
Merge pull request #847 from YosysHQ/clifford/fix785 
Fix $readmem[hb] for mem2reg memories, fixes #785
 2019-03-02 10:27:58 -08:00
Clifford Wolf 5d93dcce86 Fix $readmem[hb] for mem2reg memories, fixes #785 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 09:58:20 -08:00
Clifford Wolf f2f5ecd834
Merge pull request #843 from YosysHQ/clifford/mem2regconstidx 
Use mem2reg on memories that only have constant-index write ports
 2019-03-02 08:40:54 -08:00
Clifford Wolf 67b78ea4fb
Merge pull request #845 from YosysHQ/clifford/travisnomacos 
Disable macOS builds in Travis
 2019-03-02 08:40:17 -08:00
Clifford Wolf f75aee87e3 Disable macOS builds in Travis 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 08:29:28 -08:00
Larry Doolittle 57f8bb471f Try again for passes/pmgen/ice40_dsp_pm.h rule 
Tested on both in-tree and out-of-tree builds
 2019-03-01 20:20:53 -08:00
Keith Rothman 3e16f75bc6 Revert FF models to include IS_x_INVERTED parameters. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 14:41:21 -08:00
Keith Rothman 5ebeca12eb Use singular for disabling of DRAM or BRAM inference. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 14:35:14 -08:00
Clifford Wolf a02d61576e Minor improvements in README 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-01 14:29:17 -08:00
Clifford Wolf 7cfae2c52f Use mem2reg on memories that only have constant-index write ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-01 13:35:09 -08:00
Clifford Wolf 03237de686 Fix "write_edif -gndvccy" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-01 12:59:07 -08:00
Keith Rothman eccaf101d8 Modify arguments to match existing style. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 12:14:27 -08:00
Keith Rothman 3090951d54 Changes required for VPR place and route synth_xilinx. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 12:02:27 -08:00
Clifford Wolf 66fd6396d4
Merge pull request #841 from mmicko/master 
Fix ECP5 cells_sim for iverilog
 2019-03-01 10:53:23 -08:00
Miodrag Milanovic ca2b3feed8 Fix ECP5 cells_sim for iverilog 2019-03-01 19:25:23 +01:00