Clifford Wolf
|
d7763634b6
|
After reading the SV spec, using non-standard predict() instead of expect()
|
2016-07-21 13:34:33 +02:00 |
Clifford Wolf
|
721f1f5ecf
|
Added basic support for $expect cells
|
2016-07-13 16:56:17 +02:00 |
Clifford Wolf
|
0d2923cccd
|
Connections between inputs and inouts are driven by the input
|
2016-04-26 19:49:05 +02:00 |
Clifford Wolf
|
0bc95f1e04
|
Added "yosys -D" feature
|
2016-04-21 23:28:37 +02:00 |
Clifford Wolf
|
d6592d5b99
|
Use alphanumerical order instead of idstring idx in opt_clean compare_signals()
|
2016-02-02 09:16:18 +01:00 |
Clifford Wolf
|
ae09c89f62
|
Fixed opt_clean handling of inout ports
|
2015-08-16 09:50:17 +02:00 |
Clifford Wolf
|
c43f38c81b
|
Improved handling of "keep" attributes in hierarchical designs in opt_clean
|
2015-08-12 14:10:14 +02:00 |
Clifford Wolf
|
667b015018
|
Merge pull request #70 from gaomy3832/bugfix
Remove unused blackbox modules in opt_clean.
|
2015-08-12 08:45:04 +02:00 |
Mingyu Gao
|
cbda56d178
|
Remove unused blackbox modules in opt_clean.
|
2015-08-11 09:51:08 -07:00 |
Clifford Wolf
|
2185125760
|
Added missing ct_all setup to opt_clean
|
2015-08-11 07:54:32 +02:00 |
Clifford Wolf
|
6c84341f22
|
Fixed trailing whitespaces
|
2015-07-02 11:14:30 +02:00 |
Clifford Wolf
|
e122c2644e
|
preserve used $-wires with init attribute in opt_clean
|
2015-05-22 08:20:29 +02:00 |
Clifford Wolf
|
1f1deda888
|
Added non-std verilog assume() statement
|
2015-02-26 18:47:39 +01:00 |
Clifford Wolf
|
9ae21263f0
|
Some cleanups in "clean"
|
2015-02-24 22:31:30 +01:00 |
Clifford Wolf
|
910556560f
|
Added $meminit cell type
|
2015-02-14 10:23:03 +01:00 |
Clifford Wolf
|
8805c24640
|
Fixed opt_clean performance bug
|
2015-02-04 16:34:06 +01:00 |
Clifford Wolf
|
a8f4a099b5
|
Using design->selected_modules() in opt_*
|
2015-02-03 23:45:01 +01:00 |
Clifford Wolf
|
43951099cf
|
Added dict/pool.sort()
|
2015-01-24 00:13:27 +01:00 |
Clifford Wolf
|
3ff0d04555
|
Cleanups in opt_clean
|
2014-12-29 05:11:06 +01:00 |
Clifford Wolf
|
7d843adef9
|
dict/pool changes in opt_clean
|
2014-12-29 04:06:52 +01:00 |
Clifford Wolf
|
3da46d3437
|
Renamed hashmap.h to hashlib.h, some related improvements
|
2014-12-28 17:51:16 +01:00 |
Clifford Wolf
|
66ab88d7b0
|
More hashtable finetuning
|
2014-12-27 03:04:50 +01:00 |
Clifford Wolf
|
ec4751e55c
|
Replaced std::unordered_set (nodict) with Yosys::pool
|
2014-12-26 21:59:41 +01:00 |
Clifford Wolf
|
a6c96b986b
|
Added Yosys::{dict,nodict,vector} container types
|
2014-12-26 10:53:21 +01:00 |
Clifford Wolf
|
84ffe04075
|
Fixed various VS warnings
|
2014-10-18 15:20:38 +02:00 |
Clifford Wolf
|
66eb254fc2
|
Some cleanups in opt_clean
|
2014-10-16 11:46:57 +02:00 |
Clifford Wolf
|
4569a747f8
|
Renamed SIZE() to GetSize() because of name collision on Win32
|
2014-10-10 17:07:24 +02:00 |
Clifford Wolf
|
c3e779a65f
|
Added $_BUF_ cell type
|
2014-10-03 10:12:28 +02:00 |
Clifford Wolf
|
600c6cb013
|
remove buffers in opt_clean
|
2014-10-03 10:04:15 +02:00 |
Clifford Wolf
|
0b8cfbc6fd
|
Added support for "keep" on modules
|
2014-09-29 12:51:54 +02:00 |
Clifford Wolf
|
f9a307a50b
|
namespace Yosys
|
2014-09-27 16:17:53 +02:00 |
Ruben Undheim
|
79cbf9067c
|
Corrected spelling mistakes found by lintian
|
2014-09-06 08:47:06 +02:00 |
Clifford Wolf
|
2a1b08aeb3
|
Added design->scratchpad
|
2014-08-30 19:37:12 +02:00 |
Clifford Wolf
|
ca87116449
|
More idstring sort_by_* helpers and fixed tpl ordering in techmap
|
2014-08-15 02:40:46 +02:00 |
Clifford Wolf
|
b9bd22b8c8
|
More cleanups related to RTLIL::IdString usage
|
2014-08-02 13:19:57 +02:00 |
Clifford Wolf
|
7bd2d1064f
|
Using log_assert() instead of assert()
|
2014-07-28 11:27:48 +02:00 |
Clifford Wolf
|
0c86d6106c
|
Added SigPool::check(bit)
|
2014-07-27 15:38:02 +02:00 |
Clifford Wolf
|
77a1462f2d
|
Fixed bug in opt_clean
|
2014-07-27 15:13:29 +02:00 |
Clifford Wolf
|
dbb3556e3f
|
Fixed a bug in opt_clean and some RTLIL API usage cleanups
|
2014-07-27 13:19:05 +02:00 |
Clifford Wolf
|
10e5791c5e
|
Refactoring: Renamed RTLIL::Design::modules to modules_
|
2014-07-27 11:18:30 +02:00 |
Clifford Wolf
|
4c4b602156
|
Refactoring: Renamed RTLIL::Module::cells to cells_
|
2014-07-27 01:51:45 +02:00 |
Clifford Wolf
|
f9946232ad
|
Refactoring: Renamed RTLIL::Module::wires to wires_
|
2014-07-27 01:49:51 +02:00 |
Clifford Wolf
|
946ddff9ce
|
Changed a lot of code to the new RTLIL::Wire constructors
|
2014-07-26 20:12:50 +02:00 |
Clifford Wolf
|
f8fdc47d33
|
Manual fixes for new cell connections API
|
2014-07-26 15:58:23 +02:00 |
Clifford Wolf
|
b7dda72302
|
Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
|
2014-07-26 15:58:23 +02:00 |
Clifford Wolf
|
cc4f10883b
|
Renamed RTLIL::{Module,Cell}::connections to connections_
|
2014-07-26 11:58:03 +02:00 |
Clifford Wolf
|
2bec47a404
|
Use only module->addCell() and module->remove() to create and delete cells
|
2014-07-25 17:56:19 +02:00 |
Clifford Wolf
|
6aa792c864
|
Replaced more old SigChunk programming patterns
|
2014-07-24 23:10:58 +02:00 |
Clifford Wolf
|
c094c53de8
|
Removed RTLIL::SigSpec::optimize()
|
2014-07-23 20:32:28 +02:00 |
Clifford Wolf
|
a62c21c9c6
|
Removed RTLIL::SigSpec::expand() method
|
2014-07-23 19:34:51 +02:00 |
Clifford Wolf
|
ec923652e2
|
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
|
2014-07-23 09:52:55 +02:00 |
Clifford Wolf
|
a8d3a68971
|
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
|
2014-07-23 09:49:43 +02:00 |
Clifford Wolf
|
4b4048bc5f
|
SigSpec refactoring: using the accessor functions everywhere
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
a233762a81
|
SigSpec refactoring: renamed chunks and width to __chunks and __width
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
28e14ee50a
|
Fixed handling of "keep" attribute on wires in opt_clean
|
2014-02-16 21:58:27 +01:00 |
Clifford Wolf
|
922d1c9520
|
Only count non-trivial attributes when findinf master signal in opt_clean
|
2014-02-08 14:21:04 +01:00 |
Clifford Wolf
|
274bcef66c
|
Improved detection of primary wire for a signal in opt_clean
|
2014-02-07 23:50:17 +01:00 |
Clifford Wolf
|
1e67099b77
|
Added $assert cell
|
2014-01-19 14:03:40 +01:00 |
Clifford Wolf
|
b04051a0e2
|
Fixed keep attribute on wires in opt_clean
|
2013-11-08 05:20:15 +01:00 |
Clifford Wolf
|
1d34fd7608
|
Added support for "keep" attributes on wires
|
2013-11-05 15:52:29 +01:00 |
Clifford Wolf
|
e679a5d046
|
Fixed handling of boolean attributes (passes)
|
2013-10-24 11:37:54 +02:00 |
Clifford Wolf
|
8cc53ef72c
|
Only prefer connected signals iff they have public names
|
2013-10-17 22:10:55 +02:00 |
Clifford Wolf
|
c20571ca5e
|
Avoid re-arranging signals on register outputs
|
2013-10-17 20:48:40 +02:00 |
Clifford Wolf
|
f5c0ed6c79
|
Fixed detection of major wires in opt_clean
|
2013-10-17 02:41:59 +02:00 |
Clifford Wolf
|
96e7abad48
|
Added iopadmap pass
|
2013-10-16 16:16:06 +02:00 |
Clifford Wolf
|
a5836af172
|
Added "clean -purge" and ";;;" support
|
2013-08-11 13:59:14 +02:00 |
Clifford Wolf
|
080f0aac34
|
Added ";;" as shortcut for "; clean;"
|
2013-08-11 13:33:38 +02:00 |
Clifford Wolf
|
05483619f0
|
Some fixes to improve determinism
|
2013-08-09 12:42:32 +02:00 |
Clifford Wolf
|
8cd153612e
|
Added "clean" command (less verbose opt_clean)
|
2013-08-08 10:53:37 +02:00 |
Clifford Wolf
|
e729857647
|
Improved handling of private names in opt_clean and rename commands
|
2013-08-07 18:39:49 +02:00 |
Clifford Wolf
|
cf885c4a28
|
Added opt_clean -purge option
|
2013-07-07 12:59:30 +02:00 |
Clifford Wolf
|
c32b918681
|
Renamed opt_rmunused to opt_clean
|
2013-06-05 07:07:31 +02:00 |