yosys

Commit Graph

Author	SHA1	Message	Date
Clifford Wolf	f71e27dbf1	Remove auto_wire framework (smarter than the verilog standard)	2013-11-24 17:29:11 +01:00
Clifford Wolf	609caa23b5	Implemented correct handling of signed module parameters	2013-11-24 17:17:21 +01:00
Clifford Wolf	18d003254c	Massive performance improvement from refactoring RTLIL::SigSpec::optimize()	2013-11-22 04:41:20 +01:00
Clifford Wolf	8e58bb330d	Added SigBit struct and refactored RTLIL::SigSpec::extract	2013-11-22 04:07:13 +01:00
Clifford Wolf	0fd3ebdb23	Added information on all internal cell types to internal checker	2013-11-11 00:13:18 +01:00
Clifford Wolf	223892ac28	Improved user-friendliness of "sat" and "eval" expression parsing	2013-11-09 12:02:27 +01:00
Clifford Wolf	947bd9b96b	Renamed extend_un0() to extend_u0() and use it in genrtlil	2013-11-07 18:17:10 +01:00
Clifford Wolf	0e1661f84e	Fixed type of sign extension in opt_const $eq/$ne handling	2013-11-07 16:53:28 +01:00
Clifford Wolf	f94266bb42	Added eval -vloghammer_report mode	2013-11-06 04:14:56 +01:00
Clifford Wolf	8e8f1994b8	Changed NEW_WIRE API to return the wire, not the signal	2013-10-18 14:19:45 +02:00
Clifford Wolf	cc5e379eca	Added RTLIL NEW_WIRE macro	2013-10-18 13:25:24 +02:00
Clifford Wolf	0f38008ed3	Added "design" command (-reset, -save, -load)	2013-07-27 14:27:51 +02:00
Clifford Wolf	21e38bed98	Added "eval" pass	2013-06-19 09:30:37 +02:00
Clifford Wolf	6971c4db62	Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API	2013-06-18 17:11:13 +02:00
Clifford Wolf	21d9251e52	Added "dump" command (part ilang backend)	2013-06-02 17:53:30 +02:00
Clifford Wolf	88af5b6a16	Improved opt_share for reduce cells	2013-03-29 11:19:21 +01:00
Clifford Wolf	041c06bd9d	Create nice errors when calling RTLIL::Module::derive() of base class	2013-03-26 19:27:49 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00

18 Commits