ee0beb481d
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto
...
ast: swap range regardless of range_left >= 0
2020-05-14 18:06:18 +02:00
ebfdf61eb9
Merge pull request #2022 from Xiretza/fallthroughs
...
Avoid switch fall-through warnings
2020-05-08 05:30:32 +00:00
0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990
...
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
2020-05-07 18:11:48 +02:00
695150b037
Add YS_FALLTHROUGH macro to mark case fall-through
...
C++17 introduced [[fallthrough]], GCC and clang had their own vendored
attributes before that. MSVC doesn't seem to have such a warning at all.
2020-05-07 13:39:34 +02:00
283b1130a6
Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup
...
frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-05 07:59:40 -07:00
e936ac61ea
ast: swap range regardless of range_left >= 0
2020-05-04 12:18:20 -07:00
22bf22fab4
frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-04 10:48:37 -07:00
eca9fc01a7
verilog: set src attribute for primitives
2020-05-04 10:22:05 -07:00
584780d776
Merge pull request #1996 from boqwxp/rtlil_source_locations
...
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
2020-05-04 08:58:50 -07:00
88185f8959
Fix handling of signed indices in bit slices
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
589ed2d970
Add AST_SELFSZ and improve handling of bit slices
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
bbbce0d1c5
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
b0268b1311
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
2020-05-01 07:17:27 +00:00
9f1fb11b1d
Clear current_scope when done with RTLIL generation, fixes #1837
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-22 14:51:20 +02:00
06a344efcb
ilang, ast: Store parameter order and default value information.
...
Fixes #1819 , #1820 .
2020-04-21 19:09:00 +02:00
9e1afde7a0
Merge pull request #1851 from YosysHQ/claire/bitselwrite
...
Improved rewrite code for writing to bit slice
2020-04-21 18:46:52 +02:00
abc8f1fcb6
Merge pull request #1961 from whitequark/paramod-original-name
...
ast, rpc: record original name of $paramod\* as \hdlname attribute
2020-04-21 01:43:20 +00:00
35990b95ec
Extend support for format strings in Verilog front-end
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-18 14:08:51 +02:00
41421f5dca
ast, rpc: record original name of $paramod\* as \hdlname attribute.
...
The $paramod name mangling is not invertible (the \ character, which
separates the module name from the parameters, is valid in the module
name itself), which does not stop people from trying to invert it.
This commit makes it easy to invert the name mangling by storing
the original name explicitly, and fixes the firrtl backend to use
the newly introduced attribute.
2020-04-18 03:47:28 +00:00
e86ba3b94d
Make mask-and-shift the default for bitselwrite
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-16 12:11:52 +02:00
e1fb12a4b9
Add LookaheadRewriter for proper bitselwrite support
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-16 12:11:07 +02:00
4d02505820
ast: Fix handling of identifiers in the global scope
...
Signed-off-by: David Shah <dave@ds0.me>
2020-04-16 10:30:07 +01:00
4711fea6c0
Improved rewrite code for writing to bit slice (disabled for now)
...
This adds the new rewrite rule. But it's still missing a check that makes
sure the new rewrite rule is actually a valid substitute in the always
block being processed. Therefore the new rewrite rule is just disabled
for now.
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-15 17:44:37 +02:00
2d436bc4f1
Merge pull request #1918 from whitequark/simplify-improve_enum
...
ast/simplify: improve enum handling
2020-04-15 14:16:50 +00:00
2106f78bb1
ast/simplify: improve enum handling.
...
Before this commit, enum values were serialized as attributes of form
\enum_<width>_<value>
where <value> was a decimal signed integer.
This has multiple drawbacks:
* Enums with large values would be hard to process for downstream
tooling that cannot parse arbitrary precision decimals. (In fact
Yosys also did not correctly process enums with large values,
and would overflow `int`.)
* Enum value attributes were not confined to their own namespace,
making it harder for downstream tooling to enumerate all such
attributes, as opposed to looking up any specific value.
* Enum values could not include x or z, which are explicitly
permitted in the SystemVerilog standard.
After this commit, enum values are serialized as attributes of form
\enum_value_<value>
where <value> is a bit sequence of the appropriate width.
2020-04-15 14:14:50 +00:00
9b4dab397e
Fix 5bba9c3, closes #1876
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-14 21:05:07 +02:00
f41c7ccfff
Merge pull request #1879 from jjj11x/jjj11x/package_decl
...
support using previously declared types/localparams/parameters in package
2020-04-14 12:40:00 +00:00
dbfd6b7530
duplicated enum item names should result in an error
2020-04-07 02:30:11 -04:00
249876b614
support using previously declared types/localparams/params in package
...
(parameters in systemverilog packages can't actually be overridden, so
allowing parameters in addition to localparams doesn't actually add any
new functionality, but it's useful to be able to use the parameter
keyword also)
2020-04-07 00:38:15 -04:00
cf716e1fff
Merge pull request #1853 from YosysHQ/eddie/fix_dynslice
...
ast: cap dynamic range select to size of signal, suppresses warnings
2020-04-02 12:27:10 -07:00
956ecd48f7
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
fdafb74eb7
kernel: use more ID::*
2020-04-02 07:14:08 -07:00
37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup
...
kernel: speedup by using more pass-by-const-ref
2020-04-02 07:13:33 -07:00
c22fb76664
ast: cap dynamic range select to size of signal, suppresses warnings
2020-04-01 09:59:23 -07:00
926a010b49
Merge pull request #1848 from YosysHQ/eddie/fix_dynslice
...
ast: simplify to fully populate dynamic slicing case transformation
2020-04-01 08:38:14 +02:00
5132f4099b
ast: simplify to fully populate dynamic slicing case transformation
2020-03-31 11:52:14 -07:00
05f74d4f31
Merge pull request #1783 from boqwxp/astcc_cleanup
...
Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
2020-03-30 13:06:10 -07:00
b538c6fbf2
Add explanatory comment about inefficient wire removal and remove superfluous call to `fixup_ports()`.
...
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-03-30 18:14:32 +00:00
1bf2bdf05b
Merge pull request #1607 from whitequark/simplify-simplify-meminit
...
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT
2020-03-27 17:28:26 +01:00
6040593994
Revert over-aggressive change to a more modest cleanup.
2020-03-27 09:46:40 +00:00
6cad865d12
Simplify was not being called for packages. Broke typedef enums.
2020-03-22 18:20:46 -07:00
43092f063f
Fix NDEBUG warnings
2020-03-19 08:48:39 -07:00
eb30d66d01
Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
2020-03-19 07:29:00 +00:00
cd82ccd258
Add precise locations for asserts
2020-03-19 10:22:07 +08:00
4555b5b819
kernel: more pass by const ref, more speedups
2020-03-18 11:21:53 -07:00
b597f85b13
Merge pull request #1718 from boqwxp/precise_locations
...
Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-03-03 08:38:32 -08:00
91892465e1
Merge pull request #1681 from YosysHQ/eddie/fix1663
...
verilog: instead of modifying localparam size, extend init constant expr
2020-03-03 08:34:31 -08:00
4f889b2f57
Merge pull request #1724 from YosysHQ/eddie/abc9_specify
...
abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
2020-03-02 12:32:27 -08:00
5bba9c3640
ast: fixes #1710 ; do not generate RTLIL for unreachable ternary
2020-02-27 16:55:55 -08:00
825b96fdcf
Comment out log()
2020-02-27 16:53:49 -08:00
Claire Wolf
whitequark
Xiretza
Eddie Hung
Claire Wolf
Alberto Gonzalez
Marcelina Kościelnicka
David Shah
Jeff Wang
Peter Crozier
huaixv