riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
5,743 Commits 92 Branches 49 Tags 39 MiB
Commit Graph

5743 Commits

Author SHA1 Message Date
Miodrag Milanovic 3b17c9018a Unify usage of noflatten among architectures 2019-01-04 11:37:25 +01:00
whitequark fd21564deb flowmap: improve debug graph output. NFC. 2019-01-04 03:30:04 +00:00
whitequark 7850a0c28a flowmap: add link to longer version of paper. NFC. 2019-01-04 02:33:10 +00:00
Clifford Wolf d98fe8ce1f
Merge pull request #775 from whitequark/opt_flowmap 
flowmap: new techmap pass
 2019-01-03 17:03:18 +01:00
whitequark 07af772a72 flowmap: new techmap pass. 2019-01-03 14:28:19 +00:00
Clifford Wolf 0fc6e2bfcf
Merge pull request #770 from whitequark/opt_expr_cmp 
opt_expr: refactor and improve simplification of comparisons
 2019-01-02 17:34:04 +01:00
whitequark bf8db55ef3 opt_expr: improve simplification of comparisons with large constants. 
The idea behind this simplification is that a N-bit signal X being
compared with an M-bit constant where M>N and the constant has Nth
or higher bit set, it either always succeeds or always fails.

However, the existing implementation only worked with one-hot signals
for some reason. It also printed incorrect messages.

This commit adjusts the simplification to have as much power as
possible, and fixes other bugs.
 2019-01-02 15:45:28 +00:00
Clifford Wolf 56ca1e6afc
Merge pull request #755 from Icenowy/anlogic-dram-init 
anlogic: implement DRAM initialization
 2019-01-02 16:28:18 +01:00
Clifford Wolf b236faffa1 Merge branch 'master' of github.com:YosysHQ/yosys 2019-01-02 15:53:50 +01:00
Clifford Wolf 979de95cf6
Merge pull request #750 from Icenowy/anlogic-ff-init 
Initialization of Anlogic DFFs
 2019-01-02 15:52:22 +01:00
Clifford Wolf 2e606b1802
Merge pull request #773 from whitequark/opt_lut_elim_fixes 
opt_lut: elimination fixes
 2019-01-02 15:45:29 +01:00
Clifford Wolf da1c8d8d3d
Merge pull request #772 from whitequark/synth_lut 
synth: add k-LUT mode
 2019-01-02 15:44:57 +01:00
Clifford Wolf 00330c741a
Merge pull request #771 from whitequark/techmap_cmp2lut 
cmp2lut: new techmap pass
 2019-01-02 15:43:10 +01:00
Clifford Wolf 1eb101a38a Improve VerificImporter support for writes to asymmetric memories 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-02 15:33:43 +01:00
Clifford Wolf 50b09de033 Fix VerificImporter asymmetric memories error message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-02 15:05:23 +01:00
Clifford Wolf 16bb823db8
Merge pull request #769 from whitequark/typos 
Fix typographical and grammatical errors and inconsistencies
 2019-01-02 14:47:18 +01:00
whitequark efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 2019-01-02 13:12:17 +00:00
whitequark c55dfb8369 opt_lut: reflect changes in sigmap. 
Otherwise, some LUTs will be missed during elimination.
 2019-01-02 10:21:58 +00:00
whitequark 06143ab33f opt_lut: use a worklist, and revisit cells affected by elimination. 2019-01-02 09:36:32 +00:00
whitequark f7363ac508 opt_lut: count eliminated cells, and set opt.did_something for them. 2019-01-02 09:14:43 +00:00
whitequark 17b2831356 synth_ice40: use 4-LUT coarse synthesis mode. 2019-01-02 08:25:55 +00:00
whitequark 18174202a9 synth: add k-LUT mode. 2019-01-02 08:25:03 +00:00
whitequark fdff32dd73 synth: improve script documentation. NFC. 2019-01-02 08:05:44 +00:00
whitequark a91892bba4 cmp2lut: new techmap pass. 2019-01-02 07:53:31 +00:00
whitequark 4fd458290c opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI. 2019-01-02 05:11:29 +00:00
whitequark 9e9846a6ea opt_expr: refactor simplification of signed X>=0 and X<0. NFCI. 2019-01-02 03:01:25 +00:00
whitequark 8e53d2e0bf opt_expr: simplify any unsigned comparisons with all-0 and all-1. 
Before this commit, only unsigned comparisons with all-0 would be
simplified. This commit also makes the code handling such comparisons
to be more rigorous and not abort on unexpected input.
 2019-01-02 02:45:49 +00:00
Clifford Wolf 4b9f619349
Merge pull request #768 from whitequark/opt_lut_elim 
opt_lut: eliminate LUTs evaluating to constants or inputs
 2019-01-01 11:13:48 +01:00
whitequark 42c356c49c opt_lut: eliminate LUTs evaluating to constants or inputs. 2018-12-31 23:55:40 +00:00
Clifford Wolf 0a840dd883 Fix handling of (* keep *) wires in wreduce 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-31 16:37:40 +01:00
Clifford Wolf e09e49ca54
Merge pull request #766 from Icenowy/anlogic-latches 
anlogic: add latch cells
 2018-12-31 15:52:01 +01:00
Larry Doolittle ebe9351f82 Fix 7 instances of add_share_file to add_gen_share_file 
in techlibs/ecp5/Makefile.inc to permit out-of-tree builds
 2018-12-29 12:53:12 +01:00
Larry Doolittle 99706b3bf4 Squelch a little more trailing whitespace 2018-12-29 12:46:54 +01:00
Icenowy Zheng 1b36944299 anlogic: add latch cells 
Add latch cells to Anlogic cells replacement library by copying other
FPGAs' latch code to it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2018-12-25 22:47:46 +08:00
Clifford Wolf 245724a504
Merge pull request #761 from whitequark/proc_clean_partial 
proc_clean: remove any empty cases, if possible to do safely
 2018-12-23 16:16:06 +01:00
Clifford Wolf 6dad191377 Add "read_ilang -[no]overwrite" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-23 15:45:09 +01:00
Clifford Wolf d938ce7ab6 Merge branch 'master' of github.com:YosysHQ/yosys 2018-12-23 15:44:19 +01:00
whitequark 18291c20d2 proc_clean: remove any empty cases if all cases use all-def compare. 2018-12-23 09:04:30 +00:00
Clifford Wolf e5eb3d2c8a
Merge pull request #757 from whitequark/manual_mem 
manual: document $meminit cell and memory_* passes
 2018-12-22 20:12:18 +01:00
whitequark b784440857 proc_clean: remove any empty cases at the end of the switch. 
Previously, only completely empty switches were removed.
 2018-12-22 09:04:46 +00:00
whitequark 182d84ad54 manual: make description of $meminit ports match reality. 2018-12-21 23:04:31 +00:00
Clifford Wolf ee8a7589e0
Merge pull request #758 from whitequark/tcl_script_args 
tcl: add support for passing arguments to scripts
 2018-12-21 17:56:43 +01:00
Clifford Wolf 29a82acb2e
Merge pull request #759 from whitequark/memory_collect_init_x 
memory_collect: do not truncate 'x from \INIT
 2018-12-21 17:39:52 +01:00
Benedikt Tutzer b9288b216d Make can now install Python libraries to system path 2018-12-21 14:08:23 +01:00
whitequark 0c318e7db5 memory_collect: do not truncate 'x from \INIT. 
The semantics of an RTLIL constant that has less bits than its
declared bit width is zero padding. Therefore, if the output of
memory_collect will be used for simulation, truncating 'x from
the end of \INIT will produce incorrect simulation results.
 2018-12-21 02:01:27 +00:00
whitequark c04908c997 manual: fix typos. 2018-12-20 07:59:40 +00:00
whitequark 2ca237e086 tcl: add support for passing arguments to scripts. 2018-12-20 07:32:24 +00:00
whitequark a9ff81dd82 manual: document $meminit cell and memory_* passes. 2018-12-20 04:54:31 +00:00
Icenowy Zheng 90d00182cf anlogic: implement DRAM initialization 
As the TD tool doesn't accept the DRAM cell to contain unknown values in
the initial value, the initialzation support of DRAM is previously
skipped.

Now add the support by add a new pass to determine unknown values in the
initial value.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2018-12-20 07:56:15 +08:00
Clifford Wolf 93d44bb9a6
Merge pull request #752 from Icenowy/anlogic-lut-cost 
Anlogic: let LUT5/6 have more cost than LUT4-
 2018-12-19 19:52:31 +01:00