Clifford Wolf
|
7ac524e8e8
|
Improved support for constant functions
|
2014-02-16 13:16:38 +01:00 |
Clifford Wolf
|
5e39e6ece2
|
Correctly convert constants to RTLIL (fixed undef handling)
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2014-02-15 15:42:10 +01:00 |
Clifford Wolf
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45d2b6ffce
|
Be more conservative with new const-function code
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2014-02-14 20:45:30 +01:00 |
Clifford Wolf
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e8af3def7f
|
Added support for FOR loops in function calls in parameters
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2014-02-14 20:33:22 +01:00 |
Clifford Wolf
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534c1a5dd0
|
Created basic support for function calls in parameter values
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2014-02-14 19:56:44 +01:00 |
Clifford Wolf
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cd9e8741a7
|
Implemented read_verilog -defer
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2014-02-13 13:59:13 +01:00 |
Clifford Wolf
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f4f230d7cc
|
Fixed gcc compiler warnings with release build
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2014-02-06 22:49:14 +01:00 |
Clifford Wolf
|
d267bcde4e
|
Fixed bug in sequential sat proofs and improved handling of asserts
|
2014-02-04 12:46:16 +01:00 |
Clifford Wolf
|
a6750b3753
|
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
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2014-02-03 13:01:45 +01:00 |
Clifford Wolf
|
d06258f74f
|
Added constant size expression support of sized constants
|
2014-02-01 13:50:23 +01:00 |
Clifford Wolf
|
4df7e03ec9
|
Bugfix in name resolution with generate blocks
|
2014-01-30 15:01:28 +01:00 |
Clifford Wolf
|
375c4dddc1
|
Added read_verilog -icells option
|
2014-01-29 00:59:28 +01:00 |
Clifford Wolf
|
88fbdd4916
|
Fixed algorithmic complexity of AST simplification of long expressions
|
2014-01-20 20:25:20 +01:00 |
Clifford Wolf
|
1e67099b77
|
Added $assert cell
|
2014-01-19 14:03:40 +01:00 |
Clifford Wolf
|
9a1eb45c75
|
Added Verilog parser support for asserts
|
2014-01-19 04:18:22 +01:00 |
Clifford Wolf
|
a3d94bf888
|
Fixed typo in frontends/ast/simplify.cc
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2014-01-12 21:04:42 +01:00 |
Clifford Wolf
|
fb2bf934dc
|
Added correct handling of $memwr priority
|
2014-01-03 00:22:17 +01:00 |
Clifford Wolf
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364f277afb
|
Fixed a stupid access after delete bug
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2013-12-29 20:18:22 +01:00 |
Clifford Wolf
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369bf81a70
|
Added support for non-const === and !== (for miter circuits)
|
2013-12-27 14:20:15 +01:00 |
Clifford Wolf
|
ecc30255ba
|
Added proper === and !== support in constant expressions
|
2013-12-27 13:50:08 +01:00 |
Clifford Wolf
|
891e4b5b0d
|
Keep strings as strings in const ternary and concat
|
2013-12-05 13:26:17 +01:00 |
Clifford Wolf
|
e935bb6eda
|
Added const folding support for $signed and $unsigned
|
2013-12-05 13:09:41 +01:00 |
Clifford Wolf
|
5c39948ead
|
Added AstNode::mkconst_str API
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2013-12-05 12:53:49 +01:00 |
Clifford Wolf
|
853538d78b
|
Fixed generate-for (and disabled double warning for auto-wire)
|
2013-12-04 21:33:00 +01:00 |
Clifford Wolf
|
3c220e0b32
|
Added support for $clog2 system function
|
2013-12-04 21:19:54 +01:00 |
Clifford Wolf
|
4a4a3fc337
|
Various improvements in support for generate statements
|
2013-12-04 21:06:54 +01:00 |
Clifford Wolf
|
f4b46ed31e
|
Replaced signed_parameters API with CONST_FLAG_SIGNED
|
2013-12-04 14:24:44 +01:00 |
Clifford Wolf
|
93a70959f3
|
Replaced RTLIL::Const::str with generic decoder method
|
2013-12-04 14:14:05 +01:00 |
Clifford Wolf
|
507c63d112
|
Added support for local regs in named blocks
|
2013-12-04 09:10:16 +01:00 |
Clifford Wolf
|
10aa08dca1
|
Fixed temp net name generation in rtlil process generator for abbreviated name matching
|
2013-11-28 21:47:08 +01:00 |
Clifford Wolf
|
0e52f3fa01
|
Added "src" attribute to processes
|
2013-11-28 17:37:50 +01:00 |
Clifford Wolf
|
8dafecd34d
|
Added module->avail_parameters (for advanced techmap features)
|
2013-11-24 20:29:07 +01:00 |
Clifford Wolf
|
7d9a90396d
|
Added verilog frontend -ignore_redef option
|
2013-11-24 19:57:42 +01:00 |
Clifford Wolf
|
019b301541
|
Early wire/reg/parameter width calculation in ast/simplify
|
2013-11-24 19:40:23 +01:00 |
Clifford Wolf
|
f71e27dbf1
|
Remove auto_wire framework (smarter than the verilog standard)
|
2013-11-24 17:29:11 +01:00 |
Clifford Wolf
|
609caa23b5
|
Implemented correct handling of signed module parameters
|
2013-11-24 17:17:21 +01:00 |
Clifford Wolf
|
295e352ba6
|
Renamed "placeholder" to "blackbox"
|
2013-11-22 15:01:12 +01:00 |
Clifford Wolf
|
95c94a02fc
|
Fixed async proc detection in mem2reg
|
2013-11-21 21:26:56 +01:00 |
Clifford Wolf
|
09471846c5
|
Major improvements in mem2reg and added "init" sync rules
|
2013-11-21 13:49:00 +01:00 |
Clifford Wolf
|
65ad556f3d
|
Another name resolution bugfix for generate blocks
|
2013-11-20 13:57:40 +01:00 |
Clifford Wolf
|
c4c299eb5a
|
Do not allow memory bit select on the left side of an assignment
|
2013-11-20 12:18:46 +01:00 |
Clifford Wolf
|
ac2be2d892
|
Fixed name resolution of local tasks and functions in generate block
|
2013-11-20 11:05:58 +01:00 |
Clifford Wolf
|
19dba2561e
|
Implemented part/bit select on memory read
|
2013-11-20 10:51:32 +01:00 |
Clifford Wolf
|
4f2edcf2f9
|
Fixed two bugs in mem2reg functionality in AST frontend
|
2013-11-18 19:55:12 +01:00 |
Clifford Wolf
|
79910a5547
|
Added dumping of attributes in AST frontend
|
2013-11-18 19:54:36 +01:00 |
Clifford Wolf
|
2a25e3bca3
|
Fixed parsing of default cases when not last case
|
2013-11-18 16:10:50 +01:00 |
Clifford Wolf
|
de03184150
|
Fixed mem2reg for reg usage outside always block
|
2013-11-18 12:35:41 +01:00 |
Clifford Wolf
|
e5b974fa2a
|
Cleanups and bugfixes in response to new internal cell checker
|
2013-11-11 00:39:45 +01:00 |
Clifford Wolf
|
378cc509cd
|
Call internal checker more often
|
2013-11-10 23:24:21 +01:00 |
Clifford Wolf
|
259cc1391e
|
More undef-propagation related fixes
|
2013-11-08 11:40:36 +01:00 |
Clifford Wolf
|
9f49d538e1
|
Fixed handling of different signedness in power operands
|
2013-11-08 11:06:11 +01:00 |
Clifford Wolf
|
4abc8e695a
|
Implemented const folding of ternary op with undef select
|
2013-11-08 04:44:09 +01:00 |
Clifford Wolf
|
fc6dc0d7b8
|
Fixed handling of power operator
|
2013-11-07 22:20:00 +01:00 |
Clifford Wolf
|
d7cb62ac96
|
Fixed more extend vs. extend_u0 issues
|
2013-11-07 19:20:20 +01:00 |
Clifford Wolf
|
02f4f89fdb
|
Disabled const folding of ternary op when select is undef
|
2013-11-07 18:18:16 +01:00 |
Clifford Wolf
|
947bd9b96b
|
Renamed extend_un0() to extend_u0() and use it in genrtlil
|
2013-11-07 18:17:10 +01:00 |
Clifford Wolf
|
ed4bcd52e5
|
Fixed sign handling in constants
|
2013-11-07 14:53:10 +01:00 |
Clifford Wolf
|
83a8b8b5ca
|
Fixed const folding in corner cases with parameters
|
2013-11-07 14:08:53 +01:00 |
Clifford Wolf
|
b52bf379b9
|
Fixed width detection for replicate operator
|
2013-11-07 12:43:04 +01:00 |
Clifford Wolf
|
536621a98b
|
Fixed at_zero evaluation of dynamic ranges
|
2013-11-07 11:25:19 +01:00 |
Clifford Wolf
|
f050c40519
|
Various fixes for correct parameter support
|
2013-11-07 10:02:11 +01:00 |
Clifford Wolf
|
160adccca2
|
Fixed the fix for propagation of width hints for $signed() and $unsigned()
|
2013-11-07 03:01:28 +01:00 |
Clifford Wolf
|
7fe13faefa
|
Fixed propagation of width hints for $signed() and $unsigned()
|
2013-11-06 22:41:21 +01:00 |
Clifford Wolf
|
baeca48a24
|
Additional fixes for undef propagation in concat and replicate ops
|
2013-11-06 21:16:54 +01:00 |
Clifford Wolf
|
6fcbc79b5c
|
Improved width extension with regard to undef propagation
|
2013-11-06 21:05:11 +01:00 |
Clifford Wolf
|
f2786df146
|
Another fix for early width and sign detection in ast simplifier
|
2013-11-04 21:29:36 +01:00 |
Clifford Wolf
|
d38c67f53d
|
Fixed const folding of ternary operator
|
2013-11-04 16:46:14 +01:00 |
Clifford Wolf
|
8d226da694
|
Use proper bit width ans sign extension for const folding
|
2013-11-04 15:37:09 +01:00 |
Clifford Wolf
|
1325514d33
|
Fixes for early width and sign detection in ast simplifier
|
2013-11-04 08:28:13 +01:00 |
Clifford Wolf
|
472117d532
|
further improved early width and sign detection in ast simplifier
|
2013-11-04 06:04:42 +01:00 |
Clifford Wolf
|
d2b083f5cb
|
Fixed detectSignWidthWorker (ast frontend) for AST_CONCAT
|
2013-11-03 18:56:45 +01:00 |
Clifford Wolf
|
ada80545fa
|
Behavior should be identical now to rev. 0b4a64ac6a (next: testing before constfold fixes)
|
2013-11-02 21:13:01 +01:00 |
Clifford Wolf
|
943329c1dc
|
Various ast changes for early expression width detection (prep for constfold fixes)
|
2013-11-02 13:00:17 +01:00 |
Clifford Wolf
|
23cf23418c
|
Fixed handling of boolean attributes (frontends)
|
2013-10-24 11:20:13 +02:00 |
Johann Glaser
|
6c4cbc03c2
|
Added support for notif0/notif1 primitives
|
2013-08-20 11:23:59 +02:00 |
Clifford Wolf
|
0003743432
|
Fixed width and sign detection for ** operator
|
2013-08-19 20:58:01 +02:00 |
Clifford Wolf
|
8656b1c08f
|
Added support for bufif0/bufif1 primitives
|
2013-08-19 19:50:04 +02:00 |
Clifford Wolf
|
4214561890
|
Improved ast dumping (ast/verilog frontend)
|
2013-08-19 19:49:14 +02:00 |
Clifford Wolf
|
759852914d
|
Added support for "2**n" shifter encoding
|
2013-08-12 14:47:50 +02:00 |
Clifford Wolf
|
c8763301b4
|
Added $div and $mod technology mapping
|
2013-08-09 17:09:24 +02:00 |
Clifford Wolf
|
0f38008ed3
|
Added "design" command (-reset, -save, -load)
|
2013-07-27 14:27:51 +02:00 |
Clifford Wolf
|
3650fd7fbe
|
More fixes in ternary op sign handling
|
2013-07-12 13:13:04 +02:00 |
Clifford Wolf
|
ded769c98c
|
Fixed sign handling in ternary operator
|
2013-07-12 01:15:37 +02:00 |
Clifford Wolf
|
b380c8c790
|
Another vloghammer related bugfix
|
2013-07-11 19:24:59 +02:00 |
Clifford Wolf
|
ed62fcdbe2
|
Fixed sign propagation in bit-wise operators
|
2013-07-09 23:53:55 +02:00 |
Clifford Wolf
|
5dab327b30
|
More fixes in ast expression sign/width handling
|
2013-07-09 23:41:43 +02:00 |
Clifford Wolf
|
00a6c1d9a5
|
Major redesign of expr width/sign detecion (verilog/ast frontend)
|
2013-07-09 14:31:57 +02:00 |
Clifford Wolf
|
e8da3ea7b6
|
Fixed another bug found using vloghammer
|
2013-07-07 16:49:30 +02:00 |
Clifford Wolf
|
eff68560a2
|
Fixed AST_CONSTANT node generation
|
2013-07-07 15:40:26 +02:00 |
Clifford Wolf
|
56432a920f
|
Added defparam support to Verilog/AST frontend
|
2013-07-04 14:12:33 +02:00 |
Clifford Wolf
|
0c6ffc4c65
|
More fixes for bugs found using xsthammer
|
2013-06-13 11:18:45 +02:00 |
Clifford Wolf
|
a5c30183b5
|
Sign-extension related fixes in SatGen and AST frontend
|
2013-06-10 17:10:06 +02:00 |
Clifford Wolf
|
59dd02baa2
|
Fixes and improvements in AST const folding
|
2013-06-10 13:56:03 +02:00 |
Clifford Wolf
|
db98a18edb
|
Enabled AST/Verilog front-end optimizations per default
|
2013-06-10 13:19:04 +02:00 |
Clifford Wolf
|
ed0e2f7a6f
|
Added log_assert() api
|
2013-05-24 14:38:36 +02:00 |
Clifford Wolf
|
c5ee2b306a
|
Merge branch 'bugfix'
|
2013-05-16 16:44:45 +02:00 |
Clifford Wolf
|
6cc8e848b6
|
Fixed synthesis of functions in latched blocks
|
2013-05-16 16:44:06 +02:00 |
Clifford Wolf
|
8f2d90de4f
|
Fixed handling of positional module parameters
|
2013-04-26 14:40:25 +02:00 |
Clifford Wolf
|
453a29c9f6
|
Only use sha1 checksums for names of parametric modules when the verbose form is to long
|
2013-04-26 13:13:58 +02:00 |
Clifford Wolf
|
e0c408cb4a
|
Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values
|
2013-04-13 21:19:10 +02:00 |
Clifford Wolf
|
f1a2fd966f
|
Now only use value from "initial" when no matching "always" block is found
|
2013-03-31 11:51:12 +02:00 |
Clifford Wolf
|
161565be10
|
Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
|
2013-03-31 11:19:11 +02:00 |
Clifford Wolf
|
7bfc7b61a8
|
Implemented proper handling of stub placeholder modules
|
2013-03-28 09:20:10 +01:00 |
Clifford Wolf
|
7a99349de4
|
Improvements and bugfixes for generate blocks with local signals
|
2013-03-26 11:31:34 +01:00 |
Clifford Wolf
|
6a382f2aba
|
Fixed handling of unconditional generate blocks
|
2013-03-26 09:44:54 +01:00 |
Clifford Wolf
|
227520f94d
|
Added nosync attribute and some async reset related fixes
|
2013-03-25 17:13:14 +01:00 |
Clifford Wolf
|
df9753d398
|
Added mem2reg option to verilog frontend
|
2013-03-24 11:13:32 +01:00 |
Clifford Wolf
|
3a5244e913
|
Another fix in mem2reg ast simplify logic
|
2013-03-24 10:42:08 +01:00 |
Clifford Wolf
|
bb3357c027
|
Improved mem2reg handling in ast simplifier
|
2013-03-24 09:27:01 +01:00 |
Clifford Wolf
|
e45d1c8865
|
Tiny fixes to verilog parser
|
2013-03-23 18:54:31 +01:00 |
Clifford Wolf
|
a321a5c412
|
Moved stand-alone libs to libs/ directory and added libs/subcircuit
|
2013-02-27 09:32:19 +01:00 |
Clifford Wolf
|
4f0c2862a0
|
Added support for verilog genblock[index].member syntax
|
2013-02-26 13:18:22 +01:00 |
Clifford Wolf
|
7764d0ba1d
|
initial import
|
2013-01-05 11:13:26 +01:00 |