riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
2,961 Commits 75 Branches 48 Tags 61 MiB
Commit Graph

2961 Commits

Author SHA1 Message Date
Martin Schmölzer 94502c39a7 Merge remote-tracking branch 'upstream/master' 2013-01-08 09:53:40 +01:00
Martin Schmölzer 4f6cda502d Add support for "fsm_export" synthesis attributes to fsm_export pass. 
This allows to specify the file name for exported files directly in the HDL
source via the fsm_export=... attribute on the FSM state register.

Verilog example:
    (* fsm_export="my_fsm.kiss2" *)
    reg [3:0] state;

The fsm_export pass now also accepts the option "-noauto". This causes only
FSMs with the fsm_export attribute to be exported, any other FSMs are ignored.

Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
 2013-01-08 09:43:35 +01:00
Clifford Wolf a24086d1db Added "getting started" section to README 2013-01-06 14:40:15 +01:00
Clifford Wolf ae731369dd Improvements in command shell 
- Added 'shell' command (run interactive shell from synth script)
- Added support for ; as cmd seperator as in "proc; opt"
- Fixed c++ static initialization order problem with pass register
 2013-01-06 13:50:30 +01:00
Clifford Wolf bc630ba0fa Added a:*=* syntax to select framework 2013-01-05 12:27:59 +01:00
Clifford Wolf e9fffd68e3 Added qtcreator.creator.user to top level .gitignore 2013-01-05 12:27:18 +01:00
Clifford Wolf a7988c01af Copy attributes from state signal to fsm cell 2013-01-05 11:44:47 +01:00
Clifford Wolf 9c955c4c17 More .gitignore and fixed "make mrproper" 2013-01-05 11:44:29 +01:00
Clifford Wolf 2d9cbd3b02 added more .gitignore files (make test) 2013-01-05 11:35:52 +01:00
Clifford Wolf 6543917fb8 added .gitignore files 2013-01-05 11:19:11 +01:00
Clifford Wolf 7764d0ba1d initial import 2013-01-05 11:13:26 +01:00