Eddie Hung
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4ef26d4755
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Merge remote-tracking branch 'origin/master' into xc7mux
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2019-06-28 11:09:42 -07:00 |
Eddie Hung
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9398921af1
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Refactor for one "abc_carry" attribute on module
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2019-06-27 16:07:14 -07:00 |
Eddie Hung
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6c256b8cda
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Merge origin/master
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2019-06-27 11:20:15 -07:00 |
Eddie Hung
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dbb8c8caaa
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Merge remote-tracking branch 'origin/xaig' into xc7mux
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2019-06-26 20:07:31 -07:00 |
Eddie Hung
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b7bef15b16
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Add "WE" to dist RAM's abc_scc_break
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2019-06-26 19:58:09 -07:00 |
Eddie Hung
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812469aaa3
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Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux
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2019-06-26 14:48:35 -07:00 |
Eddie Hung
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4d0014d1b1
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Cleanup abc_box_id
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2019-06-26 11:23:57 -07:00 |
Miodrag Milanovic
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ea0b6258ab
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Simulation model verilog fix
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2019-06-26 18:34:34 +02:00 |
Eddie Hung
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6095357390
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Add RAM32X1D box info
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2019-06-25 09:34:19 -07:00 |
Eddie Hung
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6f36ec8ecf
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Merge remote-tracking branch 'origin/master' into xaig
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2019-06-25 09:33:11 -07:00 |
Eddie Hung
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e1ba25d79f
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Add RAM32X1D box info
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2019-06-24 22:54:35 -07:00 |
Eddie Hung
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1564eb8b54
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Merge remote-tracking branch 'origin/xaig' into xc7mux
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2019-06-24 22:48:49 -07:00 |
Eddie Hung
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152e682bd5
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Add Xilinx dist RAM as comb boxes
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2019-06-24 21:54:01 -07:00 |
Eddie Hung
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f1675b88f6
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Merge remote-tracking branch 'origin/eddie/ram32x1d' into xc7mux
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2019-06-24 16:39:18 -07:00 |
Eddie Hung
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efd04880db
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Add RAM32X1D support
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2019-06-24 16:16:50 -07:00 |
Eddie Hung
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d54dceb547
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Merge remote-tracking branch 'origin/xaig' into xc7mux
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2019-06-22 19:44:17 -07:00 |
Eddie Hung
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65c022c257
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Remove DFF and RAMD box info for now
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2019-06-21 20:41:14 -07:00 |
Eddie Hung
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9abde12110
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Add $__XILINX_MUXF78 to preserve entire box
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2019-06-21 15:47:42 -07:00 |
Eddie Hung
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ee428f73ab
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Remove WIP ABC9 flop support
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2019-06-14 10:37:52 -07:00 |
Eddie Hung
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54379f9872
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Disable dist RAM boxes due to comb loop
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2019-06-11 12:02:51 -07:00 |
Eddie Hung
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8a708d1fdb
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Remove #ifndef ABC
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2019-06-11 12:02:31 -07:00 |
Eddie Hung
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7166dbe418
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Remove abc_flop attributes for now
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2019-06-06 14:35:38 -07:00 |
Eddie Hung
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6ed15b7890
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Update abc attributes on FD*E_1
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2019-06-05 12:33:40 -07:00 |
Eddie Hung
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b6e59741ae
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Typo
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2019-06-03 20:21:41 -07:00 |
Eddie Hung
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ebcc85b9b8
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Fix `ifndef
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2019-06-03 12:37:02 -07:00 |
Eddie Hung
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01f71085f2
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Add FD*E_1 -> FD*E techmap rules
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2019-05-31 18:11:24 -07:00 |
Eddie Hung
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1ad33c3b5a
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Remove whitebox attribute from DRAMs for now
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2019-05-30 13:07:29 -07:00 |
Eddie Hung
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fdfc18be91
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Carry in/out to be the last input/output for chains to be preserved
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2019-05-30 01:23:36 -07:00 |
Eddie Hung
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54e28eb3ea
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Re-enable lib_whitebox
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2019-05-27 23:08:55 -07:00 |
Eddie Hung
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4311b9b583
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Blackboxes
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2019-05-26 11:32:02 -07:00 |
Eddie Hung
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ae89e6ab26
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Add whitebox support to DRAM
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2019-05-23 08:58:57 -07:00 |
Eddie Hung
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ee8435b820
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Instead of MUXCY/XORCY use CARRY4 (with timing)
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2019-05-21 16:19:45 -07:00 |
Eddie Hung
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79fb291dbe
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Cleanup, call pmux2shiftx even without -nosrl
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2019-04-22 12:14:37 -07:00 |
Eddie Hung
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13ad19482f
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Merge remote-tracking branch 'origin' into xc7srl
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2019-04-20 10:41:43 -07:00 |
Keith Rothman
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1f9235ede5
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Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-04-12 09:35:15 -07:00 |
Keith Rothman
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e107ccdde8
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Fix LUT6_2 definition.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-04-09 11:43:19 -07:00 |
Keith Rothman
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5e0339855f
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Add additional cells sim models for core 7-series primatives.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-04-09 09:01:53 -07:00 |
Eddie Hung
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f1a8e8a480
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Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-14 08:59:19 -07:00 |
Keith Rothman
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3e16f75bc6
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Revert FF models to include IS_x_INVERTED parameters.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-03-01 14:41:21 -08:00 |
Keith Rothman
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3090951d54
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Changes required for VPR place and route synth_xilinx.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-03-01 12:02:27 -08:00 |
Eddie Hung
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73ddab6960
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Add SRL16 and SRL32 sim models
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2019-02-28 13:56:22 -08:00 |
Clifford Wolf
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6991c132b5
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Add Xilinx RAM64X1D and RAM128X1D simulation models
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2018-03-07 17:31:48 +01:00 |
Clifford Wolf
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853e949c0e
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Disabled (unused) Xilinx tristate buffers
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2015-02-04 16:33:59 +01:00 |
Clifford Wolf
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816fe6bbe0
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Added Xilinx example for Basys3 board
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2015-02-01 17:09:34 +01:00 |
Clifford Wolf
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909a95182b
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Fixed xilinx FDSE sim model
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2015-01-24 11:03:22 +01:00 |
Clifford Wolf
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7031231145
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Added MUXCY and XORCY support to synth_xilinx
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2015-01-17 15:39:54 +01:00 |
Clifford Wolf
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fd8c8d4fd3
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Added FF cells to xilinx/cells_sim.v
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2015-01-16 14:59:40 +01:00 |
Clifford Wolf
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38dfc5c580
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added minimalistic xilinx sim models
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2015-01-08 00:05:11 +01:00 |