yosys

Commit Graph

Author	SHA1	Message	Date
Clifford Wolf	924d9d6e86	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
Clifford Wolf	c329233f0d	Added output args to synth_ice40	2015-05-26 17:08:53 +02:00
Clifford Wolf	b00cad81d7	Towards DRAM support in Xilinx flow	2015-04-09 08:17:14 +02:00
Clifford Wolf	4389d9306e	Added Xilinx bram black-box modules	2015-04-06 08:44:30 +02:00
Clifford Wolf	c52a4cdeed	Added "dffinit", Support for initialized Xilinx DFF	2015-04-04 19:00:15 +02:00
Clifford Wolf	4d34d031f9	Added "stat" to "synth" and "synth_xilinx"	2015-02-15 13:25:15 +01:00
Clifford Wolf	881dcd8af9	Added final checks to "synth" and "synth_xilinx"	2015-02-15 13:00:00 +01:00
Clifford Wolf	bebbf2e5a4	no support for 6-series xilinx devices	2015-02-01 23:06:44 +01:00
Clifford Wolf	816fe6bbe0	Added Xilinx example for Basys3 board	2015-02-01 17:09:34 +01:00
Clifford Wolf	d29d26f882	Various cleanups in xilinx techlib	2015-01-18 19:43:54 +01:00
Clifford Wolf	279a18c9a3	Added synth_xilinx -retime -flatten	2015-01-17 20:47:18 +01:00
Clifford Wolf	7031231145	Added MUXCY and XORCY support to synth_xilinx	2015-01-17 15:39:54 +01:00
Clifford Wolf	dff8bd3b2a	Added dff2dffe to synth_xilinx	2015-01-16 15:49:15 +01:00
Clifford Wolf	b197279f3c	Added Xilinx MUXF7 and MUXF8 support	2015-01-15 13:50:04 +01:00
Clifford Wolf	153d3dd4e0	Various cleanups in synth_xilinx command	2015-01-13 13:20:32 +01:00
Clifford Wolf	4a0b3a5423	Various small improvements to synth_xilinx	2015-01-06 14:37:50 +01:00
Clifford Wolf	9ea2511fe8	Towards Xilinx bram support	2015-01-05 13:59:04 +01:00
Clifford Wolf	f9a307a50b	namespace Yosys	2014-09-27 16:17:53 +02:00
Clifford Wolf	20175afd29	Added "techmap -share_map" option	2013-11-24 19:50:25 +01:00
Clifford Wolf	4a3669d871	Added synth_xilinx command	2013-10-27 09:51:06 +01:00

21 Commits