This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
5,363
Commits
92
Branches
49
Tags
39
MiB
6ad09bfcea
Commit Graph
2 Commits
Author
SHA1
Message
Date
Diego
f9272fc56d
GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow
2019-04-12 23:40:02 -05:00
Clifford Wolf
cae5131bac
Added initial version of "synth_gowin"
2016-11-01 11:31:13 +01:00