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345 Commits

Author SHA1 Message Date
Clifford Wolf 246391200e Add FF support to wreduce 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-20 16:36:42 +01:00
whitequark 18291c20d2 proc_clean: remove any empty cases if all cases use all-def compare. 2018-12-23 09:04:30 +00:00
Ruben Undheim c50afc4246 Documentation improvements etc. 
- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
 2018-10-13 20:34:44 +02:00
Ruben Undheim 458a94059e Support for 'modports' for System Verilog interfaces 2018-10-12 21:11:48 +02:00
Ruben Undheim 75009ada3c Synthesis support for SystemVerilog interfaces 
This time doing the changes mostly in AST before RTLIL generation
 2018-10-12 21:11:36 +02:00
Benedikt Tutzer 95d65971f3 added some checks if python is enabled to make sure everything compiles if python is disabled in the makefile 2018-08-20 16:04:43 +02:00
Benedikt Tutzer bf7b73acfc Added Wrappers for: 
-IdString
-Const
-CaseRule
-SwitchRule
-SyncRule
-Process
-SigChunk
-SigBit
-SigSpec
With all their member functions as well as the remaining member
functions for Cell, Wire, Module and Design and static functions of
rtlil.h
 2018-08-13 15:18:46 +02:00
Benedikt Tutzer e7d3f3cd46 added destructors for wires and cells 2018-07-10 08:52:36 +02:00
Benedikt Tutzer 55df7fff19 removed debug output 2018-07-09 16:02:10 +02:00
Benedikt Tutzer 8ebaeecd83 multiple designs can now exist independent from each other. Cells/Wires/Modules can now move to a different parent without referencing issues 2018-07-09 15:48:06 +02:00
Clifford Wolf eb67a7532b Add $allconst and $allseq cell types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-23 13:14:47 +01:00
Clifford Wolf c80315cea4 Bugfix in hierarchy handling of blackbox module ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-05 13:28:45 +01:00
Clifford Wolf 76afff7ef6 Add RTLIL::Const::is_fully_ones() 2017-12-14 02:06:39 +01:00
Clifford Wolf 96ad688849 Add SigSpec::is_fully_ones() 2017-12-14 01:29:09 +01:00
Clifford Wolf 13eb47c692 Add src arguments to all cell creator helper functions 2017-09-09 10:16:48 +02:00
Clifford Wolf 8a66bd30c6 Update more stuff to use get_src_attribute() and set_src_attribute() 2017-09-01 12:26:55 +02:00
Jason Lowdermilk 71d43cfc08 Merge remote-tracking branch 'upstream/master' 2017-08-30 11:47:06 -06:00
Jason Lowdermilk 271e8ba7cd fix indent level 2017-08-30 11:46:41 -06:00
Clifford Wolf 8530333439 Add {get,set}_src_attribute() methods on RTLIL::AttrObject 2017-08-30 11:39:11 +02:00
Jason Lowdermilk 32c0f1193e Add support for source line tracking through synthesis phase 2017-08-29 14:46:35 -06:00
Clifford Wolf 4ba5bd12c6 Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef() 2017-08-18 11:40:08 +02:00
Clifford Wolf 05cdd58c8d Add $_ANDNOT_ and $_ORNOT_ gates 2017-05-17 09:08:29 +02:00
Clifford Wolf 5f1d0b1024 Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00
Clifford Wolf 3928482a3c Add $cover cell type and SVA cover() support 2017-02-04 14:14:26 +01:00
Clifford Wolf b54972c112 Fix RTLIL::Memory::start_offset initialization 2017-01-25 17:00:59 +01:00
Clifford Wolf 6b2c23c721 Bugfix in RTLIL::SigSpec::remove2() 2016-12-31 16:14:42 +01:00
Clifford Wolf a926a6afc2 Remember global declarations and defines accross read_verilog calls 2016-11-15 12:42:43 +01:00
Clifford Wolf bdc316db50 Added $anyseq cell type 2016-10-14 15:24:03 +02:00
Clifford Wolf 8ebba8a35f Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00
Clifford Wolf cb7dbf4070 Improvements in assertpmux 2016-09-07 12:42:16 +02:00
Clifford Wolf 6f41e5277d Removed $aconst cell type 2016-08-30 19:09:56 +02:00
Clifford Wolf eae390ae17 Removed $predict again 2016-08-28 21:35:33 +02:00
Clifford Wolf 23afeadb5e Fixed handling of transparent bram rd ports on ROMs 2016-08-27 17:06:22 +02:00
Clifford Wolf 4056312987 Added $anyconst and $aconst 2016-07-27 15:41:22 +02:00
Clifford Wolf 5c166e76e5 Added $initstate cell type and vlog function 2016-07-21 14:23:22 +02:00
Clifford Wolf d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf 721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Ruben Undheim a8200a773f A few modifications after pull request comments 
- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
 2016-06-18 14:23:38 +02:00
Ruben Undheim 178ff3e7f6 Added support for SystemVerilog packages with localparam definitions 2016-06-18 10:53:55 +02:00
Clifford Wolf 95757efb25 Improved support for $sop cells 2016-06-17 16:31:16 +02:00
Clifford Wolf 52bb1b968d Added $sop cell type and "abc -sop" 2016-06-17 13:50:09 +02:00
Clifford Wolf ba407da187 Added addBufGate module method 2016-02-02 11:26:07 +01:00
Rick Altherr 3c48de8e21 rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*) 
Converting to a pool<SigBit> is fairly expensive due to inserts somewhat
frequently causing rehashing.  Instead, walk through the pattern SigSpec
directly on a chunk-by-chunk basis and apply it to this SigSpec's
individual bits.  Using chunks for the pattern minimizes the number of
iterations in the outer loop.
 2016-01-31 09:20:16 -08:00
Rick Altherr 0265d7b100 rtlil: speed up SigSpec::sort_and_unify() 
std::set<> internally is often a red-black tree which is fairly
expensive to create but fast to lookup.  In the case of
sort_and_unify(), a set<> is constructed as a temporary object to
attempt to speed up lookups.  Being a temporarily, however, the cost of
creation far outweights the lookup improvement and is a net performance
loss.  Instead, sort the vector<> that already exists and then apply
std::unique().
 2016-01-31 09:20:16 -08:00
Rick Altherr 89dc40f162 rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*) 2016-01-31 09:20:16 -08:00
Rick Altherr cd3e1095b0 rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*) 2016-01-31 09:20:16 -08:00
Rick Altherr 43756559d8 rtlil: rewrite remove2() to avoid copying 2016-01-30 00:28:07 -08:00
Rick Altherr 12ebdef17c rtlil: duplicate remove2() for std::set<> 2016-01-29 23:06:40 -08:00
Clifford Wolf 207736b4ee Import more std:: stuff into Yosys namespace 2015-10-25 19:30:49 +01:00
Clifford Wolf 7f110e7018 renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit() 2015-10-24 22:56:40 +02:00
Clifford Wolf a1c3df7fe4 Fixed driver conflict handling (various cmds) 2015-10-24 19:23:30 +02:00
Clifford Wolf 2a0f577f83 Fixed handling of driver-driver conflicts in wreduce 2015-10-24 13:44:35 +02:00
Clifford Wolf 924d9d6e86 Added read-enable to memory model 2015-09-25 12:23:11 +02:00
Clifford Wolf d212d4d0c1 Cosmetic fix in Module::addLut() 2015-09-18 21:55:12 +02:00
Clifford Wolf ff50bc2ac3 Added $tribuf and $_TBUF_ cell types 2015-08-16 12:54:52 +02:00
Clifford Wolf 45ee2ba3b8 Fixed handling of [a-fxz?] in decimal constants 2015-08-11 11:32:37 +02:00
Clifford Wolf 8d6d5c30d9 Added WORDS parameter to $meminit 2015-07-31 10:40:09 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf caa274ada6 Added design->rename(module, new_name) 2015-06-30 01:37:59 +02:00
Clifford Wolf 99100f367d Added "rename -top new_name" 2015-06-17 09:38:56 +02:00
Clifford Wolf 4c733301e6 Fixed cstr_buf for std::string with small string optimization 2015-06-11 13:39:49 +02:00
Clifford Wolf de4f4dad3c Fixed "avail_parameters" handling in module clone/copy 2015-06-08 14:49:34 +02:00
Clifford Wolf f483dce7c2 Added $eq/$neq -> $logic_not/$reduce_bool optimization 2015-04-29 07:28:15 +02:00
Clifford Wolf 49859393bb Improved attributes API and handling of "src" attributes 2015-04-24 22:04:05 +02:00
Clifford Wolf a1c62b79d5 Avoid parameter values with size 0 ($mem cells) 2015-04-05 18:04:19 +02:00
Clifford Wolf 706631225e Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types 2015-04-05 09:45:14 +02:00
Clifford Wolf b005eedf36 Added $assume cell type 2015-02-26 18:04:10 +01:00
Clifford Wolf dcf2e24240 Added $meminit support to "memory" command 2015-02-14 12:55:03 +01:00
Clifford Wolf 910556560f Added $meminit cell type 2015-02-14 10:23:03 +01:00
Clifford Wolf 05d4223fb6 Added SigSpec::has_const() 2015-02-08 00:01:51 +01:00
Clifford Wolf dce1fae777 Added cell->known(), cell->input(portname), cell->output(portname) 2015-02-07 11:40:19 +01:00
Clifford Wolf 5b41470e15 Skip blackbox modules in design->selected_modules() 2015-02-03 23:12:23 +01:00
Clifford Wolf f80f5b721d Added "equiv_make -blacklist <file> -encfile <file>" 2015-01-31 12:08:20 +01:00
Clifford Wolf 43951099cf Added dict/pool.sort() 2015-01-24 00:13:27 +01:00
Clifford Wolf abf8398216 Progress in equiv_simple 2015-01-21 23:59:58 +00:00
Clifford Wolf 76c5d863c5 Added equiv_make command 2015-01-19 13:59:08 +01:00
Clifford Wolf e13a45ae61 Added $equiv cell type 2015-01-19 11:55:05 +01:00
Clifford Wolf b32ba6f568 Optimizing no-op cell->setPort() 2015-01-17 12:04:40 +01:00
Clifford Wolf e62d838bd4 Removed SigSpec::extend_xx() api 2015-01-01 11:41:52 +01:00
Clifford Wolf 0675098733 added hashlib::mkhash_init 2014-12-30 18:51:24 +01:00
Clifford Wolf ecd64182c5 Added "yosys -X" 2014-12-29 13:33:33 +01:00
Clifford Wolf a2226e5307 Added mkhash_xorshift() 2014-12-29 00:12:36 +01:00
Clifford Wolf 8773fd5897 Added memhasher (yosys -M) 2014-12-28 21:27:51 +01:00
Clifford Wolf f3a97b75c7 Fixed performance bug in object hashing 2014-12-28 19:03:18 +01:00
Clifford Wolf 3da46d3437 Renamed hashmap.h to hashlib.h, some related improvements 2014-12-28 17:51:16 +01:00
Clifford Wolf 6c8b0a5fd1 More dict/pool related changes 2014-12-27 12:02:57 +01:00
Clifford Wolf 66ab88d7b0 More hashtable finetuning 2014-12-27 03:04:50 +01:00
Clifford Wolf ec4751e55c Replaced std::unordered_set (nodict) with Yosys::pool 2014-12-26 21:59:41 +01:00
Clifford Wolf 9e6fb0b02c Replaced std::unordered_map as implementation for Yosys::dict 2014-12-26 21:35:22 +01:00
Clifford Wolf e52d1f9b9a Added new_dict (hashmap.h) and re-enabled code coverage counters 2014-12-26 19:28:52 +01:00
Clifford Wolf a6c96b986b Added Yosys::{dict,nodict,vector} container types 2014-12-26 10:53:21 +01:00
Clifford Wolf edb3c9d0c4 Renamed extend() to extend_xx(), changed most users to extend_u0() 2014-12-24 09:51:17 +01:00
Clifford Wolf 7775d2806f Added IdString::destruct_guard hack 2014-12-11 21:46:36 +01:00
Clifford Wolf 7d6e586df8 Added bool constructors to SigBit and SigSpec 2014-12-08 15:08:02 +01:00
Clifford Wolf bca2442c67 Added module->addDffe() and module->addDffeGate() 2014-12-08 14:59:38 +01:00
Clifford Wolf f1764b4fe9 Added $dffe cell type 2014-12-08 10:50:19 +01:00
Clifford Wolf fad9cec47b Added $_DFFE_??_ cell types 2014-12-08 10:43:38 +01:00
Clifford Wolf fe829bdbdc Added log_warning() API 2014-11-09 10:44:23 +01:00
Clifford Wolf 70b2efdb05 Added support for $readmemh/$readmemb 2014-10-26 20:33:10 +01:00
Clifford Wolf 84ffe04075 Fixed various VS warnings 2014-10-18 15:20:38 +02:00
Clifford Wolf 468ae92374 Various win32 / vs build fixes 2014-10-17 14:01:47 +02:00
Clifford Wolf 3be5fa053f Fixed RTLIL::SigSpec::parse() for out-of-range bit- and part-selects 2014-10-16 00:54:14 +02:00
Clifford Wolf 4569a747f8 Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf c3e779a65f Added $_BUF_ cell type 2014-10-03 10:12:28 +02:00
Clifford Wolf 00964f2f61 Initialize RTLIL::Const from std::vector<bool> 2014-09-19 15:50:55 +02:00
Clifford Wolf 2442eb3832 Fixed monitor notifications for removed cell 2014-09-14 17:04:39 +02:00
Clifford Wolf af0c8873bb Added $lcu cell type 2014-09-08 13:31:04 +02:00
Clifford Wolf d46bac3305 Added "$fa" cell type 2014-09-08 12:15:39 +02:00
Clifford Wolf b847ec8a0b Added $macc cell type 2014-09-06 15:47:46 +02:00
Clifford Wolf 8927aa6148 Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
Clifford Wolf da360771a1 Create a default selection stack in RTLIL::Design::Design() 2014-09-02 22:49:24 +02:00
Clifford Wolf e07698818d Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data 2014-09-01 11:36:02 +02:00
Clifford Wolf 8649b57b6f Added $lut support in test_cell, techmap, satgen 2014-08-31 17:43:31 +02:00
Clifford Wolf 2a1b08aeb3 Added design->scratchpad 2014-08-30 19:37:12 +02:00
Clifford Wolf 4724d94fbc Added $alu cell type 2014-08-30 18:59:05 +02:00
Clifford Wolf dfbd7dd15a Fixed module->addPmux() 2014-08-30 18:17:22 +02:00
Clifford Wolf eda603105e Added is_signed argument to SigSpec.as_int() and Const.as_int() 2014-08-24 15:14:00 +02:00
Clifford Wolf 5dce303a2a Changed backend-api from FILE to std::ostream 2014-08-23 13:54:21 +02:00
Clifford Wolf 98442e019d Added emscripten (emcc) support to build system and some build fixes 2014-08-22 16:20:22 +02:00
Clifford Wolf b37d70dfd7 Added mod->addGate() methods for new gate types 2014-08-19 14:26:54 +02:00
Clifford Wolf f3326a6421 Improved sig.remove2() performance 2014-08-17 02:16:56 +02:00
Clifford Wolf 7f734ecc09 Added module->uniquify() 2014-08-16 23:50:36 +02:00
Clifford Wolf 47c2637a96 Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ 2014-08-16 18:29:39 +02:00
Clifford Wolf b64b38eea2 Renamed $lut ports to follow A-Y naming scheme 2014-08-15 14:18:40 +02:00
Clifford Wolf f092b50148 Renamed $_INV_ cell type to $_NOT_ 2014-08-15 14:11:40 +02:00
Clifford Wolf 978a933b6a Added RTLIL::SigSpec::to_sigbit_map() 2014-08-14 23:14:47 +02:00
Clifford Wolf 2f44d8ccf8 Added sig.{replace,remove,extract} variants for std::{map,set} pattern 2014-08-14 22:32:18 +02:00
Clifford Wolf 1bf7a18fec Added module->ports 2014-08-14 16:22:52 +02:00
Clifford Wolf 746aac540b Refactoring of CellType class 2014-08-14 15:46:51 +02:00
Clifford Wolf 13f2f36884 RIP $safe_pmux 2014-08-14 11:39:46 +02:00
Clifford Wolf 523df73145 Added support for truncating of wires to wreduce pass 2014-08-05 14:47:03 +02:00
Clifford Wolf b6acbc82e6 Bugfix in "techmap -extern" 2014-08-02 20:54:30 +02:00
Clifford Wolf 8e7361f128 Removed at() method from RTLIL::IdString 2014-08-02 19:08:02 +02:00
Clifford Wolf 04727c7e0f No implicit conversion from IdString to anything else 2014-08-02 18:58:40 +02:00
Clifford Wolf e590ffc84d Improvements in new RTLIL::IdString implementation 2014-08-02 15:44:10 +02:00
Clifford Wolf 60f3dc9923 Implemented new reference counting RTLIL::IdString 2014-08-02 15:11:35 +02:00
Clifford Wolf b9bd22b8c8 More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
Clifford Wolf d13eb7e099 Added ModIndex helper class, some changes to RTLIL::Monitor 2014-08-01 17:14:32 +02:00
Clifford Wolf 97a17d39e2 Packed SigBit::data and SigBit::offset in a union 2014-08-01 15:25:42 +02:00
Clifford Wolf cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
Clifford Wolf cd9407404a Added RTLIL::Monitor 2014-07-31 14:45:14 +02:00
Clifford Wolf e6d33513a5 Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
Clifford Wolf 1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf 03c96f9ce7 Added "techmap -map %{design-name}" 2014-07-29 16:35:13 +02:00
Clifford Wolf 397b00252d Added $shift and $shiftx cell types (needed for correct part select behavior) 2014-07-29 16:35:13 +02:00
Clifford Wolf 3c45277ee0 Added wire->upto flag for signals such as "wire [0:7] x;" 2014-07-28 12:12:13 +02:00
Clifford Wolf 7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf d86a25f145 Added std::initializer_list<> constructor to SigSpec 2014-07-28 10:52:58 +02:00
Clifford Wolf f99495a895 Added cover() to all SigSpec constructors 2014-07-28 10:52:30 +02:00
Clifford Wolf c4bdba78cb Added proper Design->addModule interface 2014-07-27 21:12:09 +02:00