Clifford Wolf
c3e779a65f
Added $_BUF_ cell type
2014-10-03 10:12:28 +02:00
Clifford Wolf
0b8cfbc6fd
Added support for "keep" on modules
2014-09-29 12:51:54 +02:00
Clifford Wolf
f9a307a50b
namespace Yosys
2014-09-27 16:17:53 +02:00
Clifford Wolf
edf11c635a
Assert on new logic loops in "share" pass
2014-09-21 12:57:33 +02:00
Clifford Wolf
00964f2f61
Initialize RTLIL::Const from std::vector<bool>
2014-09-19 15:50:55 +02:00
Clifford Wolf
fa96cf4a16
Added new CodingReadme file (replaces CodingStyle and CHECKLISTS)
2014-09-16 11:26:44 +02:00
Clifford Wolf
b470c480e9
Added the obvious optimizations to alumacc $macc generator
2014-09-15 12:22:03 +02:00
Clifford Wolf
2442eb3832
Fixed monitor notifications for removed cell
2014-09-14 17:04:39 +02:00
Clifford Wolf
7815f81c32
Added "synth" command
2014-09-14 16:09:06 +02:00
Clifford Wolf
fcb46138ce
Simplified $fa undef model
2014-09-08 16:59:39 +02:00
Clifford Wolf
af0c8873bb
Added $lcu cell type
2014-09-08 13:31:04 +02:00
Clifford Wolf
d46bac3305
Added "$fa" cell type
2014-09-08 12:15:39 +02:00
Clifford Wolf
98e6463ca7
Added $macc eval model
2014-09-06 19:44:28 +02:00
Clifford Wolf
fa64942018
Added $macc SAT model
2014-09-06 19:44:11 +02:00
Clifford Wolf
b847ec8a0b
Added $macc cell type
2014-09-06 15:47:46 +02:00
Ruben Undheim
79cbf9067c
Corrected spelling mistakes found by lintian
2014-09-06 08:47:06 +02:00
Clifford Wolf
8927aa6148
Removed $bu0 cell type
2014-09-04 02:07:52 +02:00
Clifford Wolf
b9cb483f3e
Using $pos models for $bu0
2014-09-03 21:20:59 +02:00
Clifford Wolf
50ac284823
Fixes in $alu SAT- and eval-models
2014-09-03 13:39:46 +02:00
Clifford Wolf
da360771a1
Create a default selection stack in RTLIL::Design::Design()
2014-09-02 22:49:24 +02:00
Clifford Wolf
c38283dbd0
Small bug fixes in $not, $neg, and $shiftx models
2014-09-02 17:48:41 +02:00
Clifford Wolf
2fcf66b91d
Added ConstEval model for $alu cells
2014-09-01 16:35:46 +02:00
Clifford Wolf
bae09dca2b
Added SAT model for $alu cells
2014-09-01 16:35:25 +02:00
Clifford Wolf
e07698818d
Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data
2014-09-01 11:36:02 +02:00
Clifford Wolf
83ec3fa204
Fixed return size of const_*() eval functions
2014-08-31 18:08:26 +02:00
Clifford Wolf
be44157c0f
Added RTLIL::Const::size()
2014-08-31 18:07:48 +02:00
Clifford Wolf
a1c7d4a8e2
Added eval model for $lut cells
2014-08-31 17:43:31 +02:00
Clifford Wolf
0b6769af3f
Typo fixes in cell->*Param() API
2014-08-31 17:43:31 +02:00
Clifford Wolf
8649b57b6f
Added $lut support in test_cell, techmap, satgen
2014-08-31 17:43:31 +02:00
Clifford Wolf
2a1b08aeb3
Added design->scratchpad
2014-08-30 19:37:12 +02:00
Clifford Wolf
4724d94fbc
Added $alu cell type
2014-08-30 18:59:05 +02:00
Clifford Wolf
dfbd7dd15a
Fixed module->addPmux()
2014-08-30 18:17:22 +02:00
Clifford Wolf
eda603105e
Added is_signed argument to SigSpec.as_int() and Const.as_int()
2014-08-24 15:14:00 +02:00
Clifford Wolf
58367cd87a
Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore
2014-08-23 15:14:58 +02:00
Clifford Wolf
19cff41eb4
Changed frontend-api from FILE to std::istream
2014-08-23 15:03:55 +02:00
Clifford Wolf
5dce303a2a
Changed backend-api from FILE to std::ostream
2014-08-23 13:54:21 +02:00
Clifford Wolf
98442e019d
Added emscripten (emcc) support to build system and some build fixes
2014-08-22 16:20:22 +02:00
Clifford Wolf
a3494fa9ed
Added "plugin" command
2014-08-22 14:00:11 +02:00
Clifford Wolf
b37d70dfd7
Added mod->addGate() methods for new gate types
2014-08-19 14:26:54 +02:00
Clifford Wolf
aa7a3ed83f
Fixed proc_{self,share}_dirname error handling
2014-08-17 02:25:59 +02:00
Clifford Wolf
f3326a6421
Improved sig.remove2() performance
2014-08-17 02:16:56 +02:00
Clifford Wolf
9bacc0b54c
Added stackmap<> container
2014-08-17 00:56:47 +02:00
Clifford Wolf
410d043dd8
Renamed toposort.h to utils.h
2014-08-17 00:55:35 +02:00
Clifford Wolf
7f734ecc09
Added module->uniquify()
2014-08-16 23:50:36 +02:00
Clifford Wolf
47c2637a96
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
2014-08-16 18:29:39 +02:00
Clifford Wolf
56a30cf42c
Added CellTypes::cell_evaluable()
2014-08-16 16:17:07 +02:00
Clifford Wolf
dbdf89c705
Added log_spacer()
2014-08-16 15:34:00 +02:00
Clifford Wolf
b64b38eea2
Renamed $lut ports to follow A-Y naming scheme
2014-08-15 14:18:40 +02:00
Clifford Wolf
f092b50148
Renamed $_INV_ cell type to $_NOT_
2014-08-15 14:11:40 +02:00
Clifford Wolf
ca87116449
More idstring sort_by_* helpers and fixed tpl ordering in techmap
2014-08-15 02:40:46 +02:00
Clifford Wolf
8ff71b5ae5
Added Frontend "+/" filename syntax for files from proc_share_dir
2014-08-15 02:08:02 +02:00
Clifford Wolf
978a933b6a
Added RTLIL::SigSpec::to_sigbit_map()
2014-08-14 23:14:47 +02:00
Clifford Wolf
2f44d8ccf8
Added sig.{replace,remove,extract} variants for std::{map,set} pattern
2014-08-14 22:32:18 +02:00
Clifford Wolf
1bf7a18fec
Added module->ports
2014-08-14 16:22:52 +02:00
Clifford Wolf
746aac540b
Refactoring of CellType class
2014-08-14 15:46:51 +02:00
Clifford Wolf
13f2f36884
RIP $safe_pmux
2014-08-14 11:39:46 +02:00
Clifford Wolf
e5ac8fdf2b
Fixed SigBit(RTLIL::Wire *wire) constructor
2014-08-12 15:39:48 +02:00
Clifford Wolf
5215723c64
Another build fix by americanrouter (via reddit)
2014-08-11 15:55:41 +02:00
Clifford Wolf
0b8b8d41eb
Fixed build with gcc-4.6
2014-08-07 22:37:01 +02:00
Clifford Wolf
523df73145
Added support for truncating of wires to wreduce pass
2014-08-05 14:47:03 +02:00
Clifford Wolf
ebbbe7fc83
Added RTLIL::IdString::in(...)
2014-08-04 15:40:07 +02:00
Clifford Wolf
653edd7a2f
Added query() API to ModIndex
2014-08-03 15:00:38 +02:00
Clifford Wolf
75423169c5
Added ID() macro for static IdStrings
2014-08-03 14:59:13 +02:00
Clifford Wolf
bc947d4c7b
Fixed a va_list corruption in logv_error()
2014-08-02 21:54:30 +02:00
Clifford Wolf
b6acbc82e6
Bugfix in "techmap -extern"
2014-08-02 20:54:30 +02:00
Clifford Wolf
8e7361f128
Removed at() method from RTLIL::IdString
2014-08-02 19:08:02 +02:00
Clifford Wolf
04727c7e0f
No implicit conversion from IdString to anything else
2014-08-02 18:58:40 +02:00
Clifford Wolf
768eb846c4
More bugfixes related to new RTLIL::IdString
2014-08-02 18:14:21 +02:00
Clifford Wolf
08392aad8f
Limit size of log_signal buffer to 100 elements
2014-08-02 15:52:21 +02:00
Clifford Wolf
e590ffc84d
Improvements in new RTLIL::IdString implementation
2014-08-02 15:44:10 +02:00
Clifford Wolf
60f3dc9923
Implemented new reference counting RTLIL::IdString
2014-08-02 15:11:35 +02:00
Clifford Wolf
97ad0623df
Fixed memory corruption related to id2cstr()
2014-08-02 13:34:07 +02:00
Clifford Wolf
b9bd22b8c8
More cleanups related to RTLIL::IdString usage
2014-08-02 13:19:57 +02:00
Clifford Wolf
14412e6c95
Preparations for RTLIL::IdString redesign: cleanup of existing code
2014-08-02 00:45:25 +02:00
Clifford Wolf
75ffd1643c
Added logfile hash to statistics footer
2014-08-01 19:43:28 +02:00
Clifford Wolf
1e224506be
Added per-pass cpu usage statistics
2014-08-01 18:42:10 +02:00
Clifford Wolf
d13eb7e099
Added ModIndex helper class, some changes to RTLIL::Monitor
2014-08-01 17:14:32 +02:00
Clifford Wolf
97a17d39e2
Packed SigBit::data and SigBit::offset in a union
2014-08-01 15:25:42 +02:00
Clifford Wolf
32a1cc3efd
Renamed modwalker.h to modtools.h
2014-07-31 23:30:18 +02:00
Clifford Wolf
cdae8abe16
Renamed port access function on RTLIL::Cell, added param access functions
2014-07-31 16:38:54 +02:00
Clifford Wolf
b5a9e51b96
Added "trace" command
2014-07-31 15:02:16 +02:00
Clifford Wolf
cd9407404a
Added RTLIL::Monitor
2014-07-31 14:45:14 +02:00
Clifford Wolf
e6d33513a5
Added module->design and cell->module, wire->module pointers
2014-07-31 14:11:39 +02:00
Clifford Wolf
1cb25c05b3
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
2014-07-31 13:19:47 +02:00
Clifford Wolf
6166c76831
Added "yosys -A"
2014-07-31 01:05:27 +02:00
Clifford Wolf
e5c245df9d
Added "yosys -Q"
2014-07-31 00:53:21 +02:00
Clifford Wolf
2541489105
Added techmap CONSTMAP feature
2014-07-30 22:04:30 +02:00
Clifford Wolf
6400ae3648
Added write_file command
2014-07-30 19:59:29 +02:00
Clifford Wolf
3f0a5746ef
Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models
2014-07-30 18:37:17 +02:00
Clifford Wolf
45fd26b76e
Added "log_dump_val_worker(char *v)"
2014-07-30 15:58:21 +02:00
Clifford Wolf
a7c6b37abf
Added "kernel/yosys.h" and "kernel/yosys.cc"
2014-07-30 14:10:15 +02:00
Clifford Wolf
273383692a
Added "test_cell" command
2014-07-29 22:07:41 +02:00
Clifford Wolf
e6df25bf74
Renamed "write_autotest" to "test_autotb" and moved to passes/tests/
2014-07-29 21:12:50 +02:00
Clifford Wolf
03c96f9ce7
Added "techmap -map %{design-name}"
2014-07-29 16:35:13 +02:00
Clifford Wolf
397b00252d
Added $shift and $shiftx cell types (needed for correct part select behavior)
2014-07-29 16:35:13 +02:00
Clifford Wolf
3c45277ee0
Added wire->upto flag for signals such as "wire [0:7] x;"
2014-07-28 12:12:13 +02:00
Clifford Wolf
7bd2d1064f
Using log_assert() instead of assert()
2014-07-28 11:27:48 +02:00
Clifford Wolf
d86a25f145
Added std::initializer_list<> constructor to SigSpec
2014-07-28 10:52:58 +02:00
Clifford Wolf
f99495a895
Added cover() to all SigSpec constructors
2014-07-28 10:52:30 +02:00
Clifford Wolf
c4bdba78cb
Added proper Design->addModule interface
2014-07-27 21:12:09 +02:00
Clifford Wolf
5da343b7de
Added topological sorting to techmap
2014-07-27 16:43:39 +02:00
Clifford Wolf
0c86d6106c
Added SigPool::check(bit)
2014-07-27 15:38:02 +02:00
Clifford Wolf
ddd31a0b66
Small improvements in PerformanceTimer API
2014-07-27 15:14:02 +02:00
Clifford Wolf
d07a871d35
Improved performance of opt_const on large modules
2014-07-27 14:50:25 +02:00
Clifford Wolf
4be645860b
Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs
2014-07-27 14:47:48 +02:00
Clifford Wolf
cbc3a46a97
Added RTLIL::SigSpecConstIterator
2014-07-27 14:47:23 +02:00
Clifford Wolf
d878fcbdc7
Added log_cmd_error_expection
2014-07-27 12:05:50 +02:00
Clifford Wolf
675cb93da9
Added RTLIL::Module::wire(id) and cell(id) lookup functions
2014-07-27 11:18:31 +02:00
Clifford Wolf
0bd8fafbd2
Added RTLIL::Design::modules()
2014-07-27 11:18:30 +02:00
Clifford Wolf
10e5791c5e
Refactoring: Renamed RTLIL::Design::modules to modules_
2014-07-27 11:18:30 +02:00
Clifford Wolf
d088854b47
Added conversion from ObjRange to std::vector and std::set
2014-07-27 11:18:30 +02:00
Clifford Wolf
1c8fdaeef8
Added RTLIL::ObjIterator and RTLIL::ObjRange
2014-07-27 11:18:30 +02:00
Clifford Wolf
ddc5b41848
Using std::move() in SigSpec move constructor
2014-07-27 09:20:59 +02:00
Clifford Wolf
7f3dc86ecd
Added RTLIL::SigSpec move constructor and move assignment operator
2014-07-27 02:11:57 +02:00
Clifford Wolf
c91570bde3
Mostly cosmetic changes to rtlil.h
2014-07-27 02:00:04 +02:00
Clifford Wolf
4c4b602156
Refactoring: Renamed RTLIL::Module::cells to cells_
2014-07-27 01:51:45 +02:00
Clifford Wolf
f9946232ad
Refactoring: Renamed RTLIL::Module::wires to wires_
2014-07-27 01:49:51 +02:00
Clifford Wolf
d68c993ed2
Changed more code to the new RTLIL::Wire constructors
2014-07-26 21:30:38 +02:00
Clifford Wolf
946ddff9ce
Changed a lot of code to the new RTLIL::Wire constructors
2014-07-26 20:12:50 +02:00
Clifford Wolf
267c615640
Added support for here documents
2014-07-26 17:21:40 +02:00
Clifford Wolf
97a59851a6
Added RTLIL::Cell::has(portname)
2014-07-26 16:11:28 +02:00
Clifford Wolf
f8fdc47d33
Manual fixes for new cell connections API
2014-07-26 15:58:23 +02:00
Clifford Wolf
b7dda72302
Changed users of cell->connections_ to the new API (sed command)
...
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
2014-07-26 15:58:23 +02:00
Clifford Wolf
cd6574ecf6
Added some missing "const" in rtlil.h
2014-07-26 15:58:22 +02:00
Clifford Wolf
7ac9dc7f6e
Added RTLIL::Module::connections()
2014-07-26 15:58:21 +02:00
Clifford Wolf
b03aec6e32
Added RTLIL::Module::connect(const RTLIL::SigSig&)
2014-07-26 14:31:47 +02:00
Clifford Wolf
3719281ed4
Automatically pack SigSpec on copy/assign
2014-07-26 13:59:30 +02:00
Clifford Wolf
e75e495c2b
Added new RTLIL::Cell port access methods
2014-07-26 12:22:58 +02:00
Clifford Wolf
cc4f10883b
Renamed RTLIL::{Module,Cell}::connections to connections_
2014-07-26 11:58:03 +02:00
Clifford Wolf
4755e14e7b
Added copy-constructor-like module->addCell(name, other) method
2014-07-26 00:38:44 +02:00
Clifford Wolf
2bec47a404
Use only module->addCell() and module->remove() to create and delete cells
2014-07-25 17:56:19 +02:00
Clifford Wolf
c762050e7f
Added RTLIL::SigSpec is_chunk()/as_chunk() API
2014-07-25 14:23:10 +02:00
Clifford Wolf
c4e4f79a2a
Disabled cover() for non-linux builds
2014-07-25 12:27:36 +02:00
Clifford Wolf
7f1789ad1b
Fixed typo in cover id
2014-07-25 03:41:53 +02:00
Clifford Wolf
6aa792c864
Replaced more old SigChunk programming patterns
2014-07-24 23:10:58 +02:00
Clifford Wolf
10d2402e2f
Added cover_list() API
2014-07-24 20:47:18 +02:00
Clifford Wolf
2f54345cff
Added "cover" command
2014-07-24 16:14:19 +02:00
Clifford Wolf
e589289df7
Some improvements in SigSpec packing/unpacking and checking
2014-07-24 15:05:41 +02:00
Clifford Wolf
7679000673
Now using a dedicated ELF section for all coverage counters
2014-07-24 15:05:05 +02:00
Clifford Wolf
22ede43b3f
Small changes regarding cover() and check() in SigSpec
2014-07-24 04:46:36 +02:00
Clifford Wolf
798f713629
Added support for YOSYS_COVER_FILE env variable
2014-07-24 04:16:32 +02:00
Clifford Wolf
1b0d5fc22d
Added cover() calls to RTLIL::SigSpec methods
2014-07-24 03:50:28 +02:00
Clifford Wolf
9cf12570ba
Added support for YOSYS_COVER_DIR env variable
2014-07-24 03:49:32 +02:00
Clifford Wolf
6b1018314c
Added cover() API
2014-07-24 03:48:38 +02:00
Clifford Wolf
82fa356037
Added hashing to RTLIL::SigSpec relational and equal operators
2014-07-23 23:58:03 +02:00
Clifford Wolf
f368d792fb
Disabled RTLIL::SigSpec::check() in release builds
2014-07-23 21:42:44 +02:00
Clifford Wolf
95ac484548
Fixed release build
2014-07-23 21:38:18 +02:00
Clifford Wolf
2a41afb7b2
Added RTLIL::SigSpec::repeat()
2014-07-23 21:34:14 +02:00
Clifford Wolf
c094c53de8
Removed RTLIL::SigSpec::optimize()
2014-07-23 20:32:28 +02:00
Clifford Wolf
8fd8e4a468
Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always optimized
2014-07-23 20:11:55 +02:00
Clifford Wolf
a62c21c9c6
Removed RTLIL::SigSpec::expand() method
2014-07-23 19:34:51 +02:00
Clifford Wolf
4e802eb7f6
Fixed all users of SigSpec::chunks_rw() and removed it
2014-07-23 15:36:09 +02:00
Clifford Wolf
85db102e13
Replaced RTLIL::SigSpec::operator!=() with inline version
2014-07-23 15:35:09 +02:00
Clifford Wolf
ec923652e2
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
2014-07-23 09:52:55 +02:00
Clifford Wolf
a8d3a68971
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
2014-07-23 09:49:43 +02:00
Clifford Wolf
260c19ec5a
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3
2014-07-23 09:34:47 +02:00
Clifford Wolf
c61467a32c
Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&)
2014-07-23 08:59:54 +02:00
Clifford Wolf
115dd959d9
SigSpec refactoring: More cleanups of old SigSpec use pattern
2014-07-22 23:50:21 +02:00
Clifford Wolf
9e94f41b89
SigSpec refactoring: Added RTLIL::SigSpecIterator
2014-07-22 23:49:26 +02:00
Clifford Wolf
f80da7b41d
SigSpec refactoring: added RTLIL::SigSpec::operator[]
2014-07-22 22:54:03 +02:00
Clifford Wolf
fd4cbe6275
SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked form
2014-07-22 22:26:30 +02:00
Clifford Wolf
a97be0828a
Removed RTLIL::SigChunk::compare()
2014-07-22 21:40:52 +02:00
Clifford Wolf
08e1e25169
SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api
2014-07-22 21:33:52 +02:00
Clifford Wolf
28b3fd05fa
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
2014-07-22 20:58:44 +02:00
Clifford Wolf
7bffde6abd
SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only
2014-07-22 20:39:38 +02:00
Clifford Wolf
4b4048bc5f
SigSpec refactoring: using the accessor functions everywhere
2014-07-22 20:39:37 +02:00
Clifford Wolf
16e5ae0b92
SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and added accessor functions
2014-07-22 20:39:37 +02:00
Clifford Wolf
a233762a81
SigSpec refactoring: renamed chunks and width to __chunks and __width
2014-07-22 20:39:37 +02:00
Clifford Wolf
550ac35873
Added support for scripts with labels
2014-07-21 13:28:18 +02:00
Clifford Wolf
361e0d62ff
Replaced depricated NEW_WIRE macro with module->addWire() calls
2014-07-21 12:42:02 +02:00
Clifford Wolf
1d88f1cf9f
Removed deprecated module->new_wire()
2014-07-21 12:35:06 +02:00
Clifford Wolf
c54d1f2ad1
Bugfix in satgen for cells with wider in- than outputs.
2014-07-21 12:03:41 +02:00
Clifford Wolf
54b0f2e659
Added module->remove(), module->addWire(), module->addCell(), cell->check()
2014-07-21 12:02:55 +02:00
Clifford Wolf
caae6e19df
Added log_ping()
2014-07-21 12:01:45 +02:00
Clifford Wolf
8d04ca7d22
Added call_on_selection() and call_on_module() API
2014-07-20 15:33:06 +02:00
Clifford Wolf
e57db5e9b2
Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion
2014-07-20 11:01:04 +02:00
Clifford Wolf
efa7884026
Added SIZE() macro
2014-07-20 10:36:14 +02:00
Clifford Wolf
a6174aaf5e
Added log_cell()
2014-07-20 10:35:47 +02:00
Clifford Wolf
02f0acb3bc
Fixed log_id() memory corruption
2014-07-19 20:53:29 +02:00
Clifford Wolf
35edac0b31
Added ModWalker helper class
2014-07-19 15:33:00 +02:00
Clifford Wolf
1c288adcc0
Some "const" cleanups in SigMap
2014-07-19 15:32:39 +02:00
Clifford Wolf
a721f7d768
Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>
2014-07-18 11:36:34 +02:00
Clifford Wolf
2d69c309f9
Added function-like cell creation helpers
2014-07-18 10:27:06 +02:00
Clifford Wolf
a8cedb2257
Added log_id() helper function
2014-07-18 10:26:01 +02:00
Clifford Wolf
274c514879
Fixed RTLIL::SigSpec::append_bit() for appending constants
2014-07-17 12:10:57 +02:00
Clifford Wolf
73e0e13d2f
Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal
2014-07-16 11:38:02 +02:00
Clifford Wolf
847e2ee4a1
Use "verilog -sv" to parse .sv files
2014-07-11 13:10:51 +02:00
Clifford Wolf
e275e8eef9
Add support for cell arrays
2014-06-07 11:48:50 +02:00
Clifford Wolf
f9c1cd5edb
Improved error message for options after front-end filename arguments
2014-06-04 09:10:50 +02:00
Clifford Wolf
a5a519a9d1
workaround for OpenBSD 'stdout' implementation
2014-05-03 12:55:56 +02:00
Clifford Wolf
75a5d6bd1e
workaround for OpenBSD 'stdin' implementation
2014-05-02 13:22:26 +02:00
Clifford Wolf
d4a1b0af5b
Added support for dlatchsr cells
2014-03-31 14:14:40 +02:00
Clifford Wolf
e164edc8d1
Fixed typo in RTLIL::Module::addAdff()
2014-03-17 14:41:41 +01:00
Clifford Wolf
ef1795a1e8
Fixed typo in RTLIL::Module::{addSshl,addSshr}
2014-03-15 22:52:10 +01:00
Clifford Wolf
b7c71d92f6
Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API
2014-03-15 14:35:29 +01:00
Clifford Wolf
5da9558fa8
Added log_dump() support for generic pointers
2014-03-14 16:39:50 +01:00
Clifford Wolf
0ac915a757
Progress in Verific bindings
2014-03-14 11:46:13 +01:00
Clifford Wolf
77e5968323
Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API
2014-03-14 11:45:44 +01:00
Clifford Wolf
542afc562f
Hotfix for kernel/compatibility.h
2014-03-13 12:55:15 +01:00
Clifford Wolf
fad8558eb5
Merged OSX fixes from Siesh1oo with some modifications
2014-03-13 12:48:10 +01:00
Siesh1oo
8127d5e8c3
- kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname().
...
This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems.
- passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
2014-03-12 23:17:14 +01:00
Clifford Wolf
94c1307c26
Added libs/minisat (copy of minisat git master)
2014-03-12 10:17:51 +01:00
Clifford Wolf
91704a7853
Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
...
(see https://github.com/cliffordwolf/yosys/pull/28 )
2014-03-11 14:24:24 +01:00
Clifford Wolf
78c64a6401
Fixed a typo in RTLIL::Module::addReduce...
2014-03-10 12:07:26 +01:00
Clifford Wolf
fdef064b1d
Added RTLIL::Module::add... helper methods
2014-03-10 03:02:27 +01:00
Clifford Wolf
97710ffad5
Fixed use of frozen literals in SatGen
2014-03-06 13:08:44 +01:00
Clifford Wolf
a1bfde8c5e
Strictly zero-extend unsigned A-inputs of shift operations
2014-03-06 11:53:37 +01:00
Clifford Wolf
9e99984336
Fixed const folding of $bu0 cells
2014-02-27 04:09:32 +01:00
Clifford Wolf
aaaa604853
Added support for $bu0 to SatGen
2014-02-26 21:31:34 +01:00
Clifford Wolf
dab1612f81
Added support for Minisat::SimpSolver + ezSAT frezze() API
2014-02-23 01:35:59 +01:00
Clifford Wolf
b76528d8a5
Fixed small memory leak in Pass::call()
2014-02-23 01:28:29 +01:00
Clifford Wolf
483c99fe46
Added "design -push" and "design -pop"
2014-02-20 23:28:59 +01:00
Clifford Wolf
8f9c707a4c
Improved checking of internal cell conventions
2014-02-08 19:13:49 +01:00
Clifford Wolf
d85a6bf5d3
Added $slice and $concat to CellTypes list
2014-02-07 19:50:44 +01:00
Clifford Wolf
fc3b3c4ec3
Added $slice and $concat cell types
2014-02-07 17:44:57 +01:00
Clifford Wolf
a1ac710ab8
Stronger checking of internal cells
2014-02-07 17:39:35 +01:00
Clifford Wolf
a51a3fa2d2
Added echo command
2014-02-07 14:17:00 +01:00
Clifford Wolf
fa295a4528
Added generic RTLIL::SigSpec::parse_sel() with support for selection variables
2014-02-06 19:22:46 +01:00
Clifford Wolf
1c6dea3a0d
Added support for #-comments in same line as command
2014-02-06 14:26:39 +01:00
Clifford Wolf
19029f377b
Added support for backslash continuation in script files
2014-02-06 01:28:33 +01:00
Clifford Wolf
d267bcde4e
Fixed bug in sequential sat proofs and improved handling of asserts
2014-02-04 12:46:16 +01:00
Clifford Wolf
a6750b3753
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
2014-02-03 13:01:45 +01:00
Clifford Wolf
f9c4d33909
Added RTLIL::SigSpec::to_single_sigbit()
2014-02-02 21:35:26 +01:00
Clifford Wolf
672229eda5
Added yosys -H for command list
2014-01-30 12:32:59 +01:00
Clifford Wolf
96084e9864
Added -h command line option
2014-01-29 11:10:39 +01:00
Clifford Wolf
c36bac0e10
Added $assert support to satgen
2014-01-19 15:37:56 +01:00
Clifford Wolf
1e67099b77
Added $assert cell
2014-01-19 14:03:40 +01:00
Clifford Wolf
548d5aafa4
Some improvements in log_dump_val_worker() templates
2014-01-17 23:14:17 +01:00
Clifford Wolf
651ce67d97
Added select -assert-none and -assert-any
2014-01-17 16:34:50 +01:00
Clifford Wolf
7354a1718e
Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux
2014-01-03 17:30:50 +01:00
Clifford Wolf
eec2cd1e78
Added RTLIL::SigSpec::optimized() API
2014-01-03 02:43:31 +01:00
Clifford Wolf
fb2bf934dc
Added correct handling of $memwr priority
2014-01-03 00:22:17 +01:00
Clifford Wolf
1f80557ade
Added SAT undef model for $pmux and $safe_pmux
2014-01-02 19:58:59 +01:00
Clifford Wolf
249ef8695a
Major rewrite of "freduce" command
2014-01-02 16:52:33 +01:00
Clifford Wolf
15acf593e7
Added additional checks for A_SIGNED == B_SIGNED for cells with that constraint
2013-12-31 14:54:06 +01:00
Clifford Wolf
bf607df6d5
Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)
2013-12-29 17:39:49 +01:00
Clifford Wolf
c69c416d28
Added $bu0 cell (for easy correct $eq/$ne mapping)
2013-12-28 12:02:14 +01:00
Clifford Wolf
122b3c067b
Fixed sat handling of $eqx and $nex with unequal port widths
2013-12-27 18:11:05 +01:00
Clifford Wolf
0f5ab7649e
Small cleanup in SatGen
2013-12-27 15:18:14 +01:00
Clifford Wolf
ebf9abfeb6
Fixed sat handling of $eqx and $nex cells
2013-12-27 14:32:42 +01:00
Clifford Wolf
369bf81a70
Added support for non-const === and !== (for miter circuits)
2013-12-27 14:20:15 +01:00
Clifford Wolf
ecc30255ba
Added proper === and !== support in constant expressions
2013-12-27 13:50:08 +01:00
Clifford Wolf
2ee3ac4ba3
Added log_dump() API
2013-12-20 12:11:58 +01:00
Clifford Wolf
8a815ac741
Added "sat" undef support and "sat -set-init" options
2013-12-07 17:28:51 +01:00
Clifford Wolf
ccf083e5b0
Fixed uninitialized const flags bug
2013-12-07 16:56:34 +01:00
Clifford Wolf
5d83904746
Fixes and improvements in RTLIL::SigSpec::parse
2013-12-07 11:57:29 +01:00
Clifford Wolf
f4b46ed31e
Replaced signed_parameters API with CONST_FLAG_SIGNED
2013-12-04 14:24:44 +01:00
Clifford Wolf
93a70959f3
Replaced RTLIL::Const::str with generic decoder method
2013-12-04 14:14:05 +01:00
Clifford Wolf
a66ca0472a
Added Pass:call_newsel API
2013-12-02 12:17:04 +01:00
Clifford Wolf
905eac04f1
Added "history" command
2013-12-02 11:29:39 +01:00
Clifford Wolf
1b3a60976d
Using RTLIL::id2cstr for prompt printing
2013-11-29 11:55:18 +01:00
Clifford Wolf
61412d167f
Improvements in satgen undef handling
2013-11-25 16:50:45 +01:00
Clifford Wolf
bd65e67d8a
Improvements in satgen undef handling
2013-11-25 15:12:01 +01:00
Clifford Wolf
8c3f4b3957
Started implementing undef handling in satgen
2013-11-25 04:51:33 +01:00
Clifford Wolf
8dafecd34d
Added module->avail_parameters (for advanced techmap features)
2013-11-24 20:29:07 +01:00
Clifford Wolf
f71e27dbf1
Remove auto_wire framework (smarter than the verilog standard)
2013-11-24 17:29:11 +01:00
Clifford Wolf
609caa23b5
Implemented correct handling of signed module parameters
2013-11-24 17:17:21 +01:00
Clifford Wolf
532091afcb
Added more generic _TECHMAP_ wire mechanism to techmap pass
2013-11-23 15:58:06 +01:00
Clifford Wolf
c854ad2e7e
Some driver changes/fixes
2013-11-22 14:53:57 +01:00
Clifford Wolf
058ceda6a0
Added more performance measurement infrastructure
2013-11-22 14:08:10 +01:00
Clifford Wolf
18d003254c
Massive performance improvement from refactoring RTLIL::SigSpec::optimize()
2013-11-22 04:41:20 +01:00
Clifford Wolf
8e58bb330d
Added SigBit struct and refactored RTLIL::SigSpec::extract
2013-11-22 04:07:13 +01:00
Clifford Wolf
09471846c5
Major improvements in mem2reg and added "init" sync rules
2013-11-21 13:49:00 +01:00
Clifford Wolf
7d52eb0ddb
Added -v<level> option and some minor driver cleanups
2013-11-17 13:26:31 +01:00
Clifford Wolf
0fd3ebdb23
Added information on all internal cell types to internal checker
2013-11-11 00:13:18 +01:00
Clifford Wolf
378cc509cd
Call internal checker more often
2013-11-10 23:24:21 +01:00
Clifford Wolf
223892ac28
Improved user-friendliness of "sat" and "eval" expression parsing
2013-11-09 12:02:27 +01:00
Clifford Wolf
18f9477e95
Added verification of SAT model to "eval -vloghammer_report" command
2013-11-09 11:38:17 +01:00
Clifford Wolf
259cc1391e
More undef-propagation related fixes
2013-11-08 11:40:36 +01:00
Clifford Wolf
81b8f3292e
Removed debug log from const_pow()
2013-11-08 04:43:38 +01:00
Clifford Wolf
fc6dc0d7b8
Fixed handling of power operator
2013-11-07 22:20:00 +01:00
Clifford Wolf
d7cb62ac96
Fixed more extend vs. extend_u0 issues
2013-11-07 19:20:20 +01:00
Clifford Wolf
947bd9b96b
Renamed extend_un0() to extend_u0() and use it in genrtlil
2013-11-07 18:17:10 +01:00
Clifford Wolf
0e1661f84e
Fixed type of sign extension in opt_const $eq/$ne handling
2013-11-07 16:53:28 +01:00
Clifford Wolf
8c523ef81d
Improved undef handling in == and != for ConstEval
2013-11-06 22:25:35 +01:00
Clifford Wolf
6fcbc79b5c
Improved width extension with regard to undef propagation
2013-11-06 21:05:11 +01:00
Clifford Wolf
f839b842a2
Fixed handling of undef values in POS cells in ConstEval
2013-11-06 18:45:31 +01:00
Clifford Wolf
204572d926
Fixed handling of undef values in MUX select input in ConstEval
2013-11-06 17:33:20 +01:00
Clifford Wolf
f94266bb42
Added eval -vloghammer_report mode
2013-11-06 04:14:56 +01:00
Clifford Wolf
27fec4e77c
Fixed sign handling in const eval of sshl and sshr
2013-11-05 10:22:22 +01:00
Clifford Wolf
1dcb683fcb
Write yosys version to output files
2013-11-03 21:41:39 +01:00
Clifford Wolf
f39c0c9928
Fixed get_share_file_name() for installed yosys
2013-10-27 10:05:19 +01:00
Clifford Wolf
73e68fe323
Added API and Makefile rules for share/ files
2013-10-27 09:33:26 +01:00
Clifford Wolf
bd2c8ec886
Added design->full_selection() helper method
2013-10-27 09:30:58 +01:00
Clifford Wolf
e679a5d046
Fixed handling of boolean attributes (passes)
2013-10-24 11:37:54 +02:00
Clifford Wolf
eae43e2db4
Fixed handling of boolean attributes (kernel)
2013-10-24 10:59:27 +02:00
Clifford Wolf
8e8f1994b8
Changed NEW_WIRE API to return the wire, not the signal
2013-10-18 14:19:45 +02:00
Clifford Wolf
cc5e379eca
Added RTLIL NEW_WIRE macro
2013-10-18 13:25:24 +02:00
Clifford Wolf
e0f693cbb0
Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_
2013-10-18 12:13:34 +02:00
Clifford Wolf
5998c101a4
Added $sr, $dffsr and $dlatch cell types
2013-10-18 11:56:16 +02:00
Clifford Wolf
485e870bcd
Added version info to yosys command and added -V option
2013-08-20 09:48:12 +02:00
Clifford Wolf
a860efa8ac
Implemented same div-by-zero behavior as found in other synthesis tools
2013-08-15 21:00:06 +02:00
Clifford Wolf
78658199e6
Fixed signed div/mod in const eval (rounding and stuff)
2013-08-15 18:23:42 +02:00
Clifford Wolf
2f3da54f26
Added sat -ignore_div_by_zero switch
2013-08-15 11:40:01 +02:00
Clifford Wolf
d0e93e04d1
Added eval -brute_force_equiv_checker_x mode
2013-08-15 11:09:30 +02:00
Clifford Wolf
ccf36cb7d8
Added SAT support for $div and $mod cells
2013-08-11 16:27:15 +02:00
Clifford Wolf
a5836af172
Added "clean -purge" and ";;;" support
2013-08-11 13:59:14 +02:00
Clifford Wolf
080f0aac34
Added ";;" as shortcut for "; clean;"
2013-08-11 13:33:38 +02:00
Clifford Wolf
376150c926
Added techmap -opt mode
2013-08-09 15:20:22 +02:00
Clifford Wolf
05483619f0
Some fixes to improve determinism
2013-08-09 12:42:32 +02:00
Clifford Wolf
117489f95a
Fixed SigPool::del() method
2013-08-06 15:04:24 +02:00
Clifford Wolf
ff965424c2
Added proper deallocation of history buffer
2013-08-06 15:03:46 +02:00
Clifford Wolf
0f38008ed3
Added "design" command (-reset, -save, -load)
2013-07-27 14:27:51 +02:00
Clifford Wolf
974b6a947c
Added "help -write-web-command-reference-manual"
2013-07-26 00:01:31 +02:00
Clifford Wolf
ad9bbcbf40
Added $lut cells and abc lut mapping support
2013-07-23 16:19:34 +02:00
Clifford Wolf
7daeee340a
Fixed shift ops with large right hand side
2013-07-09 18:59:59 +02:00
Clifford Wolf
21e38bed98
Added "eval" pass
2013-06-19 09:30:37 +02:00
Clifford Wolf
a046a302f0
Fixed build with clang
2013-06-18 19:54:33 +02:00
Clifford Wolf
6971c4db62
Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API
2013-06-18 17:11:13 +02:00
Clifford Wolf
6d7b5f9064
Fixed even more ConstEval bugs found using xsthammer
2013-06-14 17:50:26 +02:00
Clifford Wolf
30db70b1ba
Added consteval testing to xsthammer and fixed bugs
2013-06-13 19:51:13 +02:00
Clifford Wolf
0c6ffc4c65
More fixes for bugs found using xsthammer
2013-06-13 11:18:45 +02:00
Clifford Wolf
bf2c149329
Another fix for a bug found using xsthammer
2013-06-12 19:09:14 +02:00
Clifford Wolf
a5c30183b5
Sign-extension related fixes in SatGen and AST frontend
2013-06-10 17:10:06 +02:00
Clifford Wolf
7d790febb0
Improvements and fixes in SAT code
2013-06-10 16:09:29 +02:00
Clifford Wolf
15ff4cc63b
Added history file read/write to driver
2013-06-10 15:42:52 +02:00
Clifford Wolf
a75b249427
Implemented temporal induction proofs in sat_solve
2013-06-09 18:07:05 +02:00
Clifford Wolf
b7ba90910d
Fixed handling of $_XOR_ in SAT generator
2013-06-09 14:01:50 +02:00
Clifford Wolf
0efde13775
Added sequential solving support to sat_solve
2013-06-09 13:35:46 +02:00
Clifford Wolf
6f330f0132
Set rl_basic_word_break_characters in shell
2013-06-09 11:51:06 +02:00
Clifford Wolf
e52c9aff1b
Improved readline tab completion
2013-06-09 01:04:23 +02:00
Clifford Wolf
bf59a28f80
Look for yosys-abc and yosys-svgviewer where the main exe is
2013-06-09 00:07:26 +02:00
Clifford Wolf
5a592b3739
Moved cmds from kernel/ to passes/cmds/
2013-06-08 23:16:36 +02:00
Clifford Wolf
23a7973094
Added support for shifter cells to SAT generator
2013-06-08 15:12:08 +02:00
Clifford Wolf
92f04eab10
Added "cd" and "ls" commands for convenience
2013-06-08 14:45:28 +02:00
Clifford Wolf
1434312fdd
Various improvements in sat_solve pass and SAT generator
2013-06-08 14:11:50 +02:00
Clifford Wolf
c681c17038
Improved auto-detection of -show signals in sat_solve
2013-06-08 09:34:36 +02:00
Clifford Wolf
56b593b91c
Improved sat generator and sat_solve pass
2013-06-07 14:37:33 +02:00
Clifford Wolf
46fbe9d262
Added SAT generator and simple sat_solve command
2013-06-07 13:59:13 +02:00
Clifford Wolf
21d9251e52
Added "dump" command (part ilang backend)
2013-06-02 17:53:30 +02:00
Clifford Wolf
ed0e2f7a6f
Added log_assert() api
2013-05-24 14:38:36 +02:00
Clifford Wolf
ccd2a93439
Added log_abort() api
2013-05-24 12:32:06 +02:00
Clifford Wolf
cbe423a1fe
Only initialize TCL interpreter when needed
2013-05-23 12:56:23 +02:00
Clifford Wolf
6a38e767ba
Added labels to "help -write-tex-command-reference-manual" output
2013-05-23 09:49:37 +02:00
Clifford Wolf
ebb155b2d5
Added support for processes to show command
2013-05-23 09:15:51 +02:00
Clifford Wolf
04996657c8
Fixed show command for constant assignments
2013-05-23 08:22:44 +02:00
Clifford Wolf
595db0d7b9
Added tcl "yosys -import" command
2013-05-02 15:27:01 +02:00
Clifford Wolf
97f783e668
Improved/simplified TCL bindings
2013-05-01 14:21:03 +02:00
Clifford Wolf
e6dca3445a
Fixed "show -format ..." command line parsing
2013-04-15 11:59:35 +02:00
Clifford Wolf
af4444e5b9
Fixed/improved handling of colored wires in show command
2013-04-01 14:58:43 +02:00
Clifford Wolf
32ee794bfb
Added support for @<set-name> in expand select ops (%x, %ci, %co)
2013-04-01 14:58:11 +02:00
Clifford Wolf
5919bf5525
Removed 4096 bytes limit for size of command from script file
2013-04-01 14:38:05 +02:00
Clifford Wolf
3ec9fa4048
Added -color <color> <selection> option to show command
2013-04-01 14:12:17 +02:00
Clifford Wolf
9b1ce98db6
Fixed "select" for "%%" stmt with emty stack
2013-03-31 18:06:27 +02:00
Clifford Wolf
b66e9fb348
Added "script" command
2013-03-31 18:05:31 +02:00
Clifford Wolf
88af5b6a16
Improved opt_share for reduce cells
2013-03-29 11:19:21 +01:00
Clifford Wolf
73fba5164f
Implemented TCL support (only via -c option at the moment)
2013-03-28 12:26:17 +01:00
Clifford Wolf
7bfc7b61a8
Implemented proper handling of stub placeholder modules
2013-03-28 09:20:10 +01:00
Clifford Wolf
92cf7ae2f7
Added check: only one module for "show" unless format is "ps"
2013-03-27 18:31:42 +01:00
Clifford Wolf
35a02ee81e
Now using SVG and yosys-svgviewer per default in show command
2013-03-27 18:14:16 +01:00
Clifford Wolf
041c06bd9d
Create nice errors when calling RTLIL::Module::derive() of base class
2013-03-26 19:27:49 +01:00
Clifford Wolf
4a7d624bef
Added hierarchy -generate command for generating skeletton modules
2013-03-25 02:14:33 +01:00
Clifford Wolf
e1a80b356e
Fixed handling of show -viewer
2013-03-24 15:21:57 +01:00
Clifford Wolf
2887e4305f
Fixed handling of internal signals in show command
2013-03-24 15:15:28 +01:00
Clifford Wolf
181b479e77
Improved show -colors color assignments
2013-03-24 13:32:56 +01:00
Clifford Wolf
bbae24bdf7
Added show -strech and renamed -widthlabels to -width
2013-03-24 13:27:11 +01:00
Clifford Wolf
f921b06fb0
Added -widthlabels options to chow command
2013-03-24 13:11:06 +01:00
Clifford Wolf
55c50dc499
Added -colors option to show command
2013-03-24 10:41:24 +01:00
Clifford Wolf
47325fb271
Added help -write-tex-command-reference-manual option
2013-03-21 11:33:56 +01:00
Clifford Wolf
8f610dca58
Added -S option for simple synthesis to gate logic
2013-03-21 09:52:21 +01:00
Clifford Wolf
91b94ef57b
Disabled the per-default dumping of ILANG code
2013-03-21 09:12:32 +01:00
Johann Glaser
15ad2db8fc
fixed a crash when lines start with whitespace
2013-03-18 20:58:47 +01:00
Johann Glaser
cd8008bda0
fixed typos
2013-03-18 07:28:31 +01:00
Clifford Wolf
35b4a2c553
Fixed gcc warnings and added error handling to shell escape
2013-03-15 10:29:25 +01:00
Clifford Wolf
89f009d171
Added additional functionality and cleanups in sigtools.h and celltypes.h
2013-03-15 10:22:23 +01:00
Clifford Wolf
3377a04bf2
Changed prefix for selection operators from # to %
2013-03-14 16:15:24 +01:00
Clifford Wolf
697cf1eb80
Added #ci and #co selection operators
2013-03-14 15:57:47 +01:00
Clifford Wolf
b35add5f8c
Added more features to #x selection operator
2013-03-14 15:35:05 +01:00
Clifford Wolf
b0f386751c
Added "select -write" command
2013-03-14 13:02:10 +01:00
Clifford Wolf
de823ce964
Added $sr cell type to celltypes.h
2013-03-14 01:08:30 +01:00
Clifford Wolf
eadf73c823
Added shell escape to command language
2013-03-10 14:05:42 +01:00
Clifford Wolf
0be19f6ca7
Fixed and improved #x selection operator
2013-03-08 10:15:15 +01:00
Clifford Wolf
79b3afa011
Added ## selection operator (union all on stack)
2013-03-08 08:47:35 +01:00
Clifford Wolf
653f0049a8
Added select -count mode
2013-03-08 08:31:12 +01:00
Clifford Wolf
8960bba9b5
Fixed parsing of select #x<num> operator
2013-03-06 19:01:08 +01:00
Clifford Wolf
f2f3e2cb19
Improved error message on failed module load
2013-03-06 18:30:45 +01:00
Clifford Wolf
b380af9d6d
Added support for loadable modules (aka plugins)
2013-03-06 11:58:07 +01:00
Clifford Wolf
334fd03e1c
Implemented much better #x select operator
2013-03-05 12:53:40 +01:00
Clifford Wolf
d4680fd5a0
Added design->select() api and use it in extract pass
2013-03-03 20:53:24 +01:00
Clifford Wolf
b9b990ca2c
Added support for #x:<num> select stmt
2013-03-03 17:41:46 +01:00
Clifford Wolf
9368c11144
Handle known inout ports as outputs in show command
2013-03-03 17:41:09 +01:00
Clifford Wolf
45bfe26f5f
Minor hotfixes (mostly gcc build fixes)
2013-03-03 13:18:37 +01:00
Clifford Wolf
65e5e1658c
Added library support to celltypes class and show pass
2013-03-03 10:36:23 +01:00
Clifford Wolf
4fcb9a7b99
Implemented general handler for selection arguments
2013-03-03 10:05:37 +01:00
Clifford Wolf
1bc0f04789
Added id2cstr API
2013-03-01 09:01:49 +01:00
Clifford Wolf
51c2b797b3
Do not unescape identifiers starting with \$
2013-03-01 01:10:11 +01:00
Clifford Wolf
7fccad92f7
Added more help messages
2013-03-01 00:36:19 +01:00
Clifford Wolf
cd71c70b4f
Improved help message for "shell" command
2013-02-28 16:53:34 +01:00
Clifford Wolf
af561800ed
Added online help for "show" and "hierarchy" commands
2013-02-28 13:59:49 +01:00
Clifford Wolf
6ac41b2bb1
Added help for command line options
2013-02-28 13:13:56 +01:00
Clifford Wolf
eb2df220df
Added help msg to select command (and minor improvements)
2013-02-28 12:51:30 +01:00
Clifford Wolf
cb592504f4
Added more help messages (extract, abc, dfflibmap)
2013-02-28 11:14:59 +01:00
Clifford Wolf
64aa9b37d6
Added "help" command
2013-02-28 10:21:55 +01:00
Clifford Wolf
a6cf02bdc7
Changed default frontend for "-" to "script" (was: "ilang")
2013-02-27 23:38:38 +01:00
Clifford Wolf
f28b6aff40
Implemented basic functionality of "extract" pass
2013-02-27 16:27:20 +01:00
Clifford Wolf
a321a5c412
Moved stand-alone libs to libs/ directory and added libs/subcircuit
2013-02-27 09:32:19 +01:00
Clifford Wolf
ae731369dd
Improvements in command shell
...
- Added 'shell' command (run interactive shell from synth script)
- Added support for ; as cmd seperator as in "proc; opt"
- Fixed c++ static initialization order problem with pass register
2013-01-06 13:50:30 +01:00
Clifford Wolf
bc630ba0fa
Added a:*=* syntax to select framework
2013-01-05 12:27:59 +01:00
Clifford Wolf
7764d0ba1d
initial import
2013-01-05 11:13:26 +01:00