4 Commits

Author	SHA1	Message	Date
Krystine Sherwin	fae35fe98b	Docs: example_synth fifo update ... More detail on `memory_libmap`, the `$__ICE40_RAM4K_` intermediate step, and the bizarre opt output.	2024-01-30 13:34:29 +13:00
Krystine Sherwin	12fa443fe3	example_synth: more on hierarchy and stat	2024-01-13 17:46:04 +13:00
Krystine Sherwin	eb5da87d52	example_synth: hardware mapping ... Filling out the hardware mapping sections, and actually highlighting the changes in schematics instead of just the memory block. Also includes Part 4 of the coarse-grain rep, looking at `memory_collect` and putting the `synth_ice40 -top fifo -run :map_ram` command in its own (sub)section. Includes a `no_rw_check` section label in `memory.rst` for reference (because I can't remember how to reference by heading). Not sure about the opt output after map_ram section which has an open TODO, and the final steps section is also still open.	2024-01-08 16:59:03 +13:00
Krystine Sherwin	9f1c445fbf	docs: work on example_synth ... Split hardware mapping from `fifo.ys` into `fifo_map.ys`. Reduces size of `fifo.out` log and allows separate yosys calls in the makefile. Some tidy up and minor changes in `fifo.ys` for better discussion. Filled out note on `clean` (changed from `opt_clean`) and introduced `;;`. Highlighted `$memrd` and added a paragraph about it. More detail on the flatten and merging of `fifo_reader` block. Brief discussion on the changes from `$memrd` to `$memrd_v2`.	2024-01-03 11:47:33 +13:00