2 Commits

Author	SHA1	Message	Date
Jannis Harder	331ac5285f	tests: Run async2sync before sat and/or sim to handle $check cells ... Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions.	2024-02-01 16:14:11 +01:00
Jannis Harder	985f4926b7	verilog: Fix const eval of unbased unsized constants ... When the verilog frontend perfomed constant evaluation of unbased unsized constants in a context-determined expression it did not properly extend them by repeating the bit value. This only affected constant evaluation and not constants that made it through unchanged to RTLIL. The latter case was already covered by tests and working before. This fixes the const-eval issue by checking the `is_unsized` flag in bitsAsConst and extending the value accordingly. The newly added test also tests the already working non-const-eval case to highlight that both cases should behave the same.	2023-04-20 12:12:50 +02:00