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1,654 Commits 89 Branches 49 Tags 38 MiB
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104 Commits

Author SHA1 Message Date
Ahmed Irfan 6460d094e5 removed unused bib 
removed unused bibitems from the appnote verilog to btor
 2014-11-03 16:24:26 +01:00
Ahmed Irfan 3dd316bdc7 corrections in appnote 2014-11-03 16:18:53 +01:00
Ahmed Irfan 6c6cdf736a appnote added 2014-11-03 13:23:35 +01:00
Clifford Wolf af0c8873bb Added $lcu cell type 2014-09-08 13:31:04 +02:00
Ruben Undheim 79cbf9067c Corrected spelling mistakes found by lintian 2014-09-06 08:47:06 +02:00
Clifford Wolf 8927aa6148 Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
Clifford Wolf 37fe7c7bdf Removed references to yosys-svgviewer from docs 2014-09-02 04:03:06 +02:00
Clifford Wolf 4724d94fbc Added $alu cell type 2014-08-30 18:59:05 +02:00
Clifford Wolf 47c2637a96 Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ 2014-08-16 18:29:39 +02:00
Clifford Wolf f092b50148 Renamed $_INV_ cell type to $_NOT_ 2014-08-15 14:11:40 +02:00
Clifford Wolf bf486002d9 Removed old doc references to $safe_pmux 2014-08-15 14:04:35 +02:00
Clifford Wolf 13f2f36884 RIP $safe_pmux 2014-08-14 11:39:46 +02:00
Clifford Wolf bd74ed7da4 Replaced sha1 implementation 2014-08-01 19:01:10 +02:00
Clifford Wolf e6d33513a5 Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
Clifford Wolf 1202f7aa4b Renamed "stdcells.v" to "techmap.v" 2014-07-31 02:32:00 +02:00
Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf 4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf 3ec785b881 Fixed manual/CHAPTER_Prog/stubnets.cc 2014-07-23 19:36:43 +02:00
Clifford Wolf a62c21c9c6 Removed RTLIL::SigSpec::expand() method 2014-07-23 19:34:51 +02:00
Clifford Wolf 73e0e13d2f Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal 2014-07-16 11:38:02 +02:00
Clifford Wolf 1c81ab49e7 small changes in presentation 2014-07-02 06:16:31 +02:00
Clifford Wolf d26561cc44 Tiny fix in presentation 2014-06-29 09:27:03 +02:00
Clifford Wolf 3a3f5d5923 Progress in presentation 2014-06-29 09:14:49 +02:00
Clifford Wolf 3e96ce8680 Progress in presentation 2014-06-26 22:05:39 +02:00
Clifford Wolf a7aea17959 Progress in presentation 2014-06-22 12:50:29 +02:00
Clifford Wolf 072604f30f fixed typo 2014-06-21 21:13:18 +02:00
Clifford Wolf b18fa95d2f Progress in presentation 2014-06-21 16:33:33 +02:00
Clifford Wolf 1a487303a0 Progress in presentation 2014-06-14 16:45:16 +02:00
Clifford Wolf 51a615b26d Progress in presentation 2014-05-06 14:42:04 +02:00
Anthony J. Bentley 154c9f8b51 Typos and grammar fixes through chapter 4. 2014-05-02 03:08:40 -06:00
Anthony J. Bentley 9c1e578afe Typos and grammar fixes through chapter 2. 2014-04-11 02:42:59 -06:00
Anthony J. Bentley 66a5da5edc POSIX find requires a path argument. 2014-04-04 16:51:27 -06:00
Clifford Wolf 79edcd4318 Progress in presentation 2014-02-21 14:59:59 +01:00
Clifford Wolf 2aff7b2a47 Progress in presentation 2014-02-21 02:13:02 +01:00
Clifford Wolf 9351e4d3ca Progress in presentation 2014-02-20 23:44:28 +01:00
Clifford Wolf b0e84802ec Progress in presentation 2014-02-20 20:44:41 +01:00
Clifford Wolf 98940260e1 Progress in presentation 2014-02-20 12:46:29 +01:00
Clifford Wolf 3d9da919d8 Progress in presentation 2014-02-18 19:51:03 +01:00
Clifford Wolf 0fbc1a59dd Progress in presentation 2014-02-17 09:45:04 +01:00
Clifford Wolf 37cbb1ca60 Progress in presentation 2014-02-16 22:31:53 +01:00
Clifford Wolf f08c71b96c Progress in presentation 2014-02-16 17:56:19 +01:00
Clifford Wolf aeb36b0b8b Progress in presentation 2014-02-16 14:32:56 +01:00
Clifford Wolf 9c29969bbc Progress in presentation 2014-02-16 13:45:47 +01:00
Clifford Wolf 4bd2d47e45 Improved "make manual" and "make clean" 2014-02-11 12:55:58 +01:00
Clifford Wolf fc3b3c4ec3 Added $slice and $concat cell types 2014-02-07 17:44:57 +01:00
Clifford Wolf 821156b6cf presentation progress 2014-02-06 14:01:43 +01:00
Clifford Wolf 7e9ba60df8 presentation progress 2014-02-05 20:06:34 +01:00