Eddie Hung
5e2562f1a2
opt_expr: add $alu tests
2020-03-19 14:57:10 -07:00
Marcin Kościelnicki
e91368a5f4
fsm_extract: Initialize celltypes with full design.
...
Fixes #1781 .
2020-03-19 18:51:21 +01:00
N. Engelhardt
e03f725ef2
Merge pull request #1774 from boqwxp/exec
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Add `exec` command to allow running shell commands from inside Yosys scripts
2020-03-19 13:14:43 +01:00
N. Engelhardt
644deb708d
fix argument order for macOS compatibility
2020-03-18 15:11:49 +01:00
Eddie Hung
9f30d7f843
opt_merge: speedup
2020-03-16 12:43:54 -07:00
Alberto Gonzalez
a09b260c01
Add test for `exec` command.
2020-03-16 07:52:58 +00:00
Miodrag Milanović
569e834df2
Merge pull request #1759 from zeldin/constant_with_comment_redux
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refixed parsing of constant with comment between size and value
2020-03-14 13:34:59 +02:00
Marcus Comstedt
dd562f29e7
Add regression tests for new handling of comments in constants
2020-03-14 11:41:09 +01:00
Miodrag Milanović
faf4ee69de
Merge pull request #1754 from boqwxp/precise_locations
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Set AST node source location in more parser rules.
2020-03-14 11:18:39 +02:00
Miodrag Milanovic
5b73e7c63a
Added back tests for logger
2020-03-13 15:00:18 +01:00
Eddie Hung
3ada82639f
verilog: add test
2020-03-11 06:51:03 -07:00
David Shah
ddcd87b577
Merge pull request #1721 from YosysHQ/dave/tribuf-unused
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deminout: Don't demote inouts with unused bits
2020-03-10 13:51:40 +00:00
Claire Wolf
a7cc4673c3
Fix partsel expr bit width handling and add test case
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-08 16:12:12 +01:00
N. Engelhardt
88494e81f5
rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors
2020-03-06 15:29:01 +01:00
Eddie Hung
3c2e910bb3
tests: extend tests/arch/run-tests.sh for defines
2020-03-05 08:08:32 -08:00
David Shah
5cae9c6e16
deminout: Don't demote inouts with unused bits
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Signed-off-by: David Shah <dave@ds0.me>
2020-03-04 18:44:38 +00:00
Claire Wolf
b597f85b13
Merge pull request #1718 from boqwxp/precise_locations
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Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-03-03 08:38:32 -08:00
Claire Wolf
879124333f
Merge pull request #1519 from YosysHQ/eddie/submod_po
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submod: several bugfixes
2020-03-03 08:19:06 -08:00
Marcelina Kościelnicka
968956badb
iopadmap: Look harder for already-present buffers. ( #1731 )
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iopadmap: Look harder for already-present buffers.
Fixes #1720 .
2020-03-02 21:40:09 +01:00
Eddie Hung
4f889b2f57
Merge pull request #1724 from YosysHQ/eddie/abc9_specify
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abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
2020-03-02 12:32:27 -08:00
Eddie Hung
5bba9c3640
ast: fixes #1710 ; do not generate RTLIL for unreachable ternary
2020-02-27 16:55:55 -08:00
Eddie Hung
a179d918ec
Revert "Fix tests/arch/xilinx/fsm.ys to count flops only"
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This reverts commit 68f903c6dd7403a4cf280cf71ee02d20345938b5.
2020-02-27 10:17:29 -08:00
Eddie Hung
f858219c4e
Cleanup tests
2020-02-27 10:17:29 -08:00
Eddie Hung
717fb492b3
Update bug1630.ys to use -lut 4 instead of lut file
2020-02-27 10:17:29 -08:00
Eddie Hung
bc97e64b21
Fix tests/arch/xilinx/fsm.ys to count flops only
2020-02-27 10:17:29 -08:00
Eddie Hung
977262c803
Update simple_abc9 tests
2020-02-27 10:17:29 -08:00
Alberto Gonzalez
f80fe8dc22
Change attribute search value to specify precise location instead of simple line number.
2020-02-24 02:41:08 +00:00
Alberto Gonzalez
2c2f092c90
Change attribute search value to specify precise location instead of simple line number.
2020-02-24 01:39:36 +00:00
Eddie Hung
760096e8d2
Merge pull request #1703 from YosysHQ/eddie/specify_improve
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Improve specify parser
2020-02-21 09:15:17 -08:00
Claire Wolf
cd044a2bb6
Merge pull request #1642 from jjj11x/jjj11x/sv-enum
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Enum support
2020-02-20 18:17:25 +01:00
Eddie Hung
1d401a7991
clean: ignore specify-s inside cells when determining whether to keep
2020-02-19 10:45:10 -08:00
Jeff Wang
d12ba42a74
add attributes for enumerated values in ilang
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- information also useful for strongly-typed enums (not implemented)
- resolves enum values in ilang part of #1594
- still need to output enums to VCD (or better yet FST) files
2020-02-17 04:42:42 -05:00
Marcin Kościelnicki
cd60f079d6
tests/aiger: Add missing .gitignore
2020-02-15 19:52:21 +01:00
Miodrag Milanović
c7af1b22ba
Merge pull request #1701 from nakengelhardt/rpc-test
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make rpc frontend unix socket test less fragile
2020-02-14 12:06:37 +01:00
Eddie Hung
d20c1dac73
verilog: ignore ranges too without -specify
2020-02-13 17:58:43 -08:00
Eddie Hung
3065d4092e
Fine tune #1699 tests
2020-02-13 15:14:58 -08:00
Eddie Hung
6b58c1820c
verilog: improve specify support when not in -specify mode
2020-02-13 13:27:15 -08:00
Eddie Hung
2e51dc1856
verilog: ignore '&&&' when not in -specify mode
2020-02-13 13:06:13 -08:00
Eddie Hung
b523ecf2f4
specify: system timing checks to accept min:typ:max triple
2020-02-13 12:42:15 -08:00
Eddie Hung
7cfdf4ffa7
verilog: fix $specify3 check
2020-02-13 12:42:04 -08:00
Eddie Hung
ebb11bcea4
iopadmap: move \init attributes from outpad output to its input
2020-02-13 12:05:14 -08:00
N. Engelhardt
c2467fdd55
make rpc frontend unix socket test less fragile
2020-02-13 20:52:22 +01:00
N. Engelhardt
e069259a53
Merge pull request #1679 from thasti/delay-parsing
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Fix crash on wire declaration with delay
2020-02-13 12:01:27 +01:00
Eddie Hung
d4ff5b2d00
Merge pull request #1670 from rodrigomelo9/master
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$readmem[hb] file inclusion is now relative to the Verilog file
2020-02-10 08:31:01 -08:00
Marcin Kościelnicki
89adef352f
xilinx: Add support for LUT RAM on LUT4-based devices.
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There are multiple other kinds of RAMs supported on these devices, but
RAM16X1D is the only dual-port one.
Fixes #1549
2020-02-07 09:03:22 +01:00
Marcin Kościelnicki
d48950d92d
xilinx: Initial support for LUT4 devices.
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Adds support for mapping logic, including LUTs, wide LUTs, and carry
chains.
Fixes #1547
2020-02-07 09:03:22 +01:00
whitequark
081d9318bc
ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
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This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
2020-02-06 16:52:51 +00:00
whitequark
3f4460a186
ice40: match memory inference attribute values case insensitive.
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LSE/Synplify use case insensitive matching.
2020-02-06 14:58:20 +00:00
whitequark
fc28bf55aa
ice40: add support for both 1364.1 and LSE RAM/ROM attributes.
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This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify appear to interpret attribute values insensitive
to case. There is currently no way to do this in Yosys (attrmap
can only change case of attribute names).
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
2020-02-06 14:58:20 +00:00
whitequark
29d130dee9
ice40: remove impossible test.
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iCE40 does not have LUTRAM. This was erroneously added in commit
caab66111e
, and tested for BRAM,
essentially a duplicate of the "dpram.ys" test.
2020-02-06 14:58:20 +00:00
Rodrigo Alejandro Melo
9da5936c05
Added 'set -e' into tests/memfile/run-test.sh
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Also added two checks for situations where the execution must fail.
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-06 10:45:40 -03:00
Eddie Hung
4c1d3a126d
shiftx2mux: fix select out of bounds
2020-02-05 16:41:09 -08:00
Eddie Hung
505557e93e
Merge pull request #1576 from YosysHQ/eddie/opt_merge_init
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opt_merge: discard \init of '$' cells with 'Q' port when merging
2020-02-05 14:56:26 -08:00
Eddie Hung
6eb7e925a1
Merge pull request #1650 from YosysHQ/eddie/shiftx2mux
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techmap LSB-first for compatible $shift/$shiftx cells
2020-02-05 14:55:57 -08:00
Eddie Hung
0b308c6835
abc9_ops: -reintegrate to use derived_type for box_ports
2020-02-05 14:46:48 -08:00
Eddie Hung
b6a1f627b5
Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux
2020-02-05 10:47:31 -08:00
Eddie Hung
5ebdc0f8e0
Merge pull request #1638 from YosysHQ/eddie/fix1631
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clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
2020-02-05 19:31:18 +01:00
Stefan Biereigel
90c78f1f85
add testcase for #1614
2020-02-03 21:29:54 +01:00
Rodrigo A. Melo
665a967d87
Merge branch 'master' into master
2020-02-03 11:07:51 -03:00
Marcelina Kościelnicka
34d2fbd2f9
Add opt_lut_ins pass. ( #1673 )
2020-02-03 14:57:17 +01:00
Rodrigo Alejandro Melo
313a425bd5
Merge branch 'master' of https://github.com/YosysHQ/yosys
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Solved a conflict into the CHANGELOG
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-03 10:56:41 -03:00
David Shah
ebe1d7d5ab
sv: More tests for wildcard port connections
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
7e741714df
hierarchy: Correct handling of wildcard port connections with default values
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
a210675d71
sv: Add tests for wildcard port connections
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
Rodrigo Alejandro Melo
8217f579b7
Removed 'synth' into tests/memfile/run-test.sh
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-02 12:34:27 -03:00
Rodrigo Alejandro Melo
9b49f1bc46
Added content1.dat into tests/memfile
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Modified run-test.sh to use it.
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-02 12:18:34 -03:00
David Shah
9f5613100b
Merge pull request #1647 from YosysHQ/dave/sprintf
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ast: Add support for $sformatf system function
2020-02-02 14:53:46 +00:00
Rodrigo Alejandro Melo
eaaba6e091
Added tests/memfile to 'make test' with an extra testcase
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-01 22:44:06 -03:00
Rodrigo Alejandro Melo
43396fae2c
Added a test for the Memory Content File inclusion using $readmemb
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-01 17:41:10 -03:00
Eddie Hung
136842b1ef
Merge branch 'master' into eddie/submod_po
2020-02-01 02:14:19 -08:00
Miodrag Milanović
71d148bcaa
Merge pull request #1559 from YosysHQ/efinix_test_fix
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Fix for non-deterministic test
2020-01-29 11:18:06 +01:00
Eddie Hung
d004953772
Add "help -all" and "help -celltypes" sanity test
2020-01-28 18:11:34 -08:00
Eddie Hung
a855f23f22
Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init
2020-01-28 12:46:18 -08:00
Eddie Hung
7939727d14
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts
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Unpermute LUT ordering for ice40/ecp5/xilinx
2020-01-28 11:55:51 -08:00
Miodrag Milanovic
94191a93dd
Updated test to use assert-max
2020-01-28 18:26:10 +01:00
Claire Wolf
4ddaa70fd6
Merge pull request #1567 from YosysHQ/eddie/sat_init_warning
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sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
2020-01-28 17:40:28 +01:00
N. Engelhardt
086c133ea5
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate
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synth_xilinx: error out if tristate without '-iopad'
2020-01-28 17:24:54 +01:00
Eddie Hung
cfb0366a18
Import tests from #1628
2020-01-27 13:56:16 -08:00
Eddie Hung
48f3f5213e
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor
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Refactor `abc9` pass
2020-01-27 13:29:15 -08:00
Eddie Hung
af8281d2f5
Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warnings
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ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
2020-01-27 09:54:04 -08:00
Eddie Hung
b178761551
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
2020-01-24 11:59:48 -08:00
Eddie Hung
2d795fb8c0
simple_abc9 tests to discard whitebox before write for sim
2020-01-23 22:07:43 -08:00
Eddie Hung
dca1c806ec
simple_abc9 tests to discard whitebox before write for sim
2020-01-23 19:55:11 -08:00
Eddie Hung
e471b330ac
abc_box_id -> abc9_box_id in test
2020-01-23 19:12:19 -08:00
Eddie Hung
11e50c0e9e
Test for (* keep *)-ed abc9_box_id
2020-01-23 18:56:25 -08:00
Eddie Hung
48aec34e0d
abc_box_id -> abc9_box_id in test
2020-01-23 18:53:14 -08:00
Eddie Hung
5aaa19f1ab
Update tests with reduced area
2020-01-21 16:50:04 -08:00
Eddie Hung
3d9737c1bd
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-21 16:27:40 -08:00
Eddie Hung
8d1b736c4f
Move from +/shiftx2mux.v into +/techmap.v; cleanup
2020-01-21 15:19:41 -08:00
Eddie Hung
7977574995
New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC
2020-01-21 15:19:41 -08:00
Eddie Hung
cd8f55a911
write_xaiger: fix for (* keep *) on flop output
2020-01-21 09:43:04 -08:00
David Shah
22c967e35e
ast: Add support for $sformatf system function
...
Signed-off-by: David Shah <dave@ds0.me>
2020-01-19 21:20:17 +00:00
Eddie Hung
6a163b5ddd
xilinx_dsp: another typo; move xilinx specific test
2020-01-17 17:07:03 -08:00
Eddie Hung
db68e4c2a7
ice40_dsp: fix typo
2020-01-17 16:08:04 -08:00
Eddie Hung
5507c328ff
Add #1644 testcase
2020-01-17 15:57:52 -08:00
Eddie Hung
ad6c49fff1
ice40_dsp: add test
2020-01-17 15:38:26 -08:00
Jeff Wang
8ef5c7d48c
scoped enum tests
2020-01-16 18:13:30 -05:00
Jeff Wang
caf35896da
enum in package test
2020-01-16 18:09:03 -05:00
Jeff Wang
febe7706a2
simple enum test
2020-01-16 18:09:03 -05:00
Eddie Hung
2245afa142
More rigorous test
2020-01-16 09:15:42 -08:00
Eddie Hung
03ce2c72bb
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-15 16:42:16 -08:00
Eddie Hung
5918ede9bd
abc9: aAdd test to check $_NOT_s are absorbed
2020-01-15 14:36:05 -08:00
Eddie Hung
e30b6bbbf8
clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
2020-01-15 09:51:31 -08:00
Eddie Hung
53a99ade9c
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-14 11:46:56 -08:00
Eddie Hung
61ffd2d199
Merge pull request #1633 from YosysHQ/eddie/fix_autoname
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autoname: do not rename ports
2020-01-14 11:40:54 -08:00
Eddie Hung
9fa0e03cc9
Merge pull request #1632 from YosysHQ/eddie/fix1630
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read_aiger: uniquify wires with $aiger<autoidx> prefix
2020-01-14 11:40:40 -08:00
Miodrag Milanović
9fbeb57bbd
Merge pull request #1623 from YosysHQ/mmicko/edif_attr
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Export wire properties in EDIF
2020-01-14 19:19:32 +01:00
Eddie Hung
00964e999d
autoname: add testcase with $-prefix-ed port
2020-01-14 10:13:03 -08:00
Eddie Hung
565d349dc9
Add #1630 testcase
2020-01-13 21:27:53 -08:00
Eddie Hung
a6d4ea7463
abc9: respect (* keep *) on cells
2020-01-13 19:21:11 -08:00
Eddie Hung
9ec948f396
write_xaiger: add support and test for (* keep *) on wires
2020-01-13 19:07:55 -08:00
Eddie Hung
ca2f3db53f
Merge pull request #1620 from YosysHQ/eddie/abc9_scratchpad
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abc9: add some scripts/options into "scratchpad"
2020-01-13 09:04:20 -08:00
Eddie Hung
ae619ba87a
Add #1626 testcase
2020-01-12 15:21:26 -08:00
Eddie Hung
c063436eea
Merge remote-tracking branch 'origin/master' into eddie/abc9_scratchpad
2020-01-11 17:02:20 -08:00
Miodrag Milanovic
ccfe1e5909
this one is fine
2020-01-10 15:20:50 +01:00
Miodrag Milanovic
af852a0ea8
Fix tests
2020-01-10 14:48:01 +01:00
Eddie Hung
a10016ccc5
Add abc9 sanity test
2020-01-09 18:17:06 -08:00
Eddie Hung
94ab3791ce
Merge remote-tracking branch 'origin/master' into eddie/abc9_mfs
2020-01-07 15:44:18 -08:00
Eddie Hung
0d3f10d3cc
Add testcases
2020-01-07 11:44:20 -08:00
Eddie Hung
7c878bf397
tests/aiger: write Yosys output
2020-01-07 11:44:03 -08:00
Eddie Hung
3df869cc7c
Add testcase from #1459
2020-01-06 16:22:22 -08:00
Eddie Hung
6e866030c2
Combine tests to check multiple clock domains
2020-01-02 14:38:59 -08:00
Eddie Hung
b454735bea
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-02 12:44:06 -08:00
Eddie Hung
9e5ff30d05
Merge pull request #1606 from YosysHQ/eddie/improve_tests
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Fix a few issues in tests/arch/*
2020-01-01 13:31:46 -08:00
Eddie Hung
52fe1e0c44
Revert insertion of 'reg', leave note behind
2020-01-01 09:05:46 -08:00
Miodrag Milanovic
a1344ec06e
Added a test case
2020-01-01 16:24:30 +01:00
Eddie Hung
713484fa66
Do not do call equiv_opt when no sim model exists
2019-12-31 18:40:30 -08:00
Eddie Hung
a59016b146
Fix warnings
2019-12-31 18:40:11 -08:00
Eddie Hung
c082329af3
Call equiv_opt with -multiclock and -assert
2019-12-31 18:39:32 -08:00
Eddie Hung
ccc0a740d2
Add some abc9 dff tests
2019-12-31 16:16:05 -08:00
Eddie Hung
0c4be94a02
Add -D DFF_MODE to abc9_map test
2019-12-30 20:13:25 -08:00
Eddie Hung
fc4b8b8991
Remove submod changes
2019-12-30 14:56:14 -08:00
Eddie Hung
405e974fe5
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-30 14:31:42 -08:00
Miodrag Milanović
c0a17c2457
Merge pull request #1589 from YosysHQ/iopad_default
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Make iopad option default for all xilinx flows
2019-12-30 20:34:31 +01:00
Eddie Hung
c2c74f9bb0
Merge pull request #1599 from YosysHQ/eddie/retry_1588
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Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once"
2019-12-30 10:01:02 -08:00
Miodrag Milanovic
f9749c202c
Fix new tests
2019-12-28 16:43:19 +01:00
Miodrag Milanovic
8c3de1d4bd
Merge remote-tracking branch 'origin/master' into iopad_default
2019-12-28 16:23:31 +01:00
Miodrag Milanovic
a82c701668
Make test without iopads
2019-12-28 16:22:24 +01:00
Miodrag Milanovic
509da7ed1a
Revert "Fix xilinx tests, when iopads are default"
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This reverts commit 477e43d921
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2019-12-28 16:12:45 +01:00
Eddie Hung
011f749ecf
Update resource count
2019-12-28 02:15:11 -08:00
Eddie Hung
d45869855c
Add #1598 testcase
2019-12-27 16:44:57 -08:00
Marcin Kościelnicki
a24596def3
iopadmap: Emit tristate buffers with const OE for some edge cases.
2019-12-25 17:37:58 +01:00
Eddie Hung
2e21aa59a2
Add DSP cascade tests
2019-12-23 14:58:06 -08:00
Marcin Kościelnicki
666c6128a9
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
Miodrag Milanovic
436fea9e69
Addressed review comments
2019-12-21 20:23:23 +01:00
Miodrag Milanovic
477e43d921
Fix xilinx tests, when iopads are default
2019-12-21 13:18:44 +01:00
Eddie Hung
1ea1e8e54f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-20 13:56:13 -08:00
Eddie Hung
94f15f023c
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-19 10:29:40 -08:00
Eddie Hung
d406f2ffd7
Merge pull request #1569 from YosysHQ/eddie/fix_1531
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verilog: preserve size of $genval$-s in for loops
2019-12-19 12:21:33 -05:00
Eddie Hung
d675f22f4e
Merge pull request #1571 from YosysHQ/eddie/fix_1570
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mem_arst.v: do not redeclare ANSI port
2019-12-19 12:21:22 -05:00