riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
11,378 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

1 Commits

Author SHA1 Message Date
Icenowy Zheng c2b7ad3b28 anlogic: support BRAM mapping 
Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being
true dual port (or 18bit*512 when simple dual port), the other is
16bit*2K.

Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and
32Kbit BRAM with 8bit width are not support yet.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2021-12-17 20:28:22 +08:00