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1938 Commits

Author SHA1 Message Date
Martin Povišer 69a36aec3b Add keep_hierarchy test 2024-11-05 09:28:45 +01:00
Krystine Sherwin ee73a91f44
Remove references to ilang 2024-11-05 12:36:31 +13:00
Lofty 3250f2b82b
Merge pull request #4700 from povik/select-list-mod 
Add `select -list-mod`
 2024-11-04 15:38:42 +00:00
Martin Povišer d752ca4847 Fix test after option change 2024-11-04 16:26:46 +01:00
Martin Povišer f7400a06cd Fix test 2024-11-04 16:19:59 +01:00
Martin Povišer 23922faecc Test new Tcl methods 2024-11-04 16:18:50 +01:00
Martin Povišer c9ed6d8dcf cellmatch: Rename `-lut_attrs` to `-derive_luts`; document option 2024-11-04 14:28:40 +01:00
Martin Povišer 7aa3fdab80 select: Add `-list-mod` option 2024-11-04 13:16:13 +01:00
Martin Povišer 9432e972f7
Merge pull request #4626 from povik/select-t-at 
select: Add new `t:@<name>` syntax
 2024-10-16 10:18:05 +02:00
Emil J. Tywoniak f9f509bc25 select: add t:@<name> test 2024-10-15 21:06:06 +02:00
Emil J. Tywoniak 785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Miodrag Milanović ecec156965
Merge pull request #4643 from donn/fix_wheels 
wheels: fix missing yosys-abc/share directory
 2024-10-09 18:05:58 +02:00
Emil J 038e262332
Merge pull request #4624 from YosysHQ/emil/cxxrtl-smoke-test 
cxxrtl: test stream operator
 2024-10-09 05:57:13 -07:00
Mohamed Gaber 3d6b8b8e1a
wheels: fix missing yosys-abc/share directory 
* `misc/__init__.py`:
  * checks if there's a `yosys-abc` in the same directory - if yes, sets the variable `sys._pyosys_abc`
  * checks if there's a `share` in the same directory - if yes, sets the variable `sys._pyosys_share_dirname`
* `yosys.cc::init_share_dirname`: check for `sys._pyosys_share_dirname`, use it at the highest priority if Python is enabled
* `yosys.cc::init_abc_executable_name`: check for `sys._pyosys_abc`, use it at at the highest priority if Python is enabled
* `Makefile`: add new target, `share`, to only create the extra targets
* `setup.py`: compile libyosys.so, yosys-abc and share, and copy them all as part of the pyosys build
* `test/arch/ecp5/add_sub.py`: ported `add_sub.ys` to Python to act as a test for the share directory and abc with Python wheels, used in CI
 2024-10-09 13:09:14 +03:00
Martin Povišer e46cc57cc4
Merge pull request #4613 from povik/err-never-silence 
log: Never silence `log_cmd_error`
 2024-10-07 16:12:31 +02:00
Martin Povišer 0aab8b4158
Merge pull request #4605 from povik/liberty-unit-delay 
read_liberty: Optionally import unit delay arcs
 2024-10-07 16:11:51 +02:00
Martin Povišer 74e92d10e8
Merge pull request #4593 from povik/aiger2 
New aiger backend
 2024-10-07 16:11:25 +02:00
Martin Povišer 6c1450fdaf
Merge pull request #4607 from povik/ql-nodiv 
quicklogic: Avoid carry chains in division mapping
 2024-10-07 16:11:11 +02:00
Martin Povišer ca5c2fdff1 quicklogic: Relax the LUT number test 2024-10-07 15:27:03 +02:00
Martin Povišer b01b17689e Add test of error not getting silenced 2024-10-07 14:49:17 +02:00
Martin Povišer d0a11e26f3 aiger2: Add test of writing a flattened view 2024-10-07 12:04:33 +02:00
Lofty 13ecbd5c76 quicklogic: test that dividing by a constant does not infer carry chains 2024-10-03 20:05:28 +01:00
Roland Coeurjoly 5ea2c6e6e5 Assume x values for missing signal data in FST 
Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-10-02 12:08:48 +02:00
Emil J. Tywoniak 997cb30f1f cxxrtl: test stream operator 2024-10-01 13:25:07 +02:00
Roland Coeurjoly 76c615b2ae Fix: handle VCD variable references with and without whitespace 
Co-authored-by: Miodrag Milanović <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-10-01 11:51:20 +02:00
rherveille ce7db661a8
Added cast to type support (#4284) 2024-09-29 17:03:01 -04:00
George Rennie 0572f8806f opt_reduce: add test for constant $reduce_and/or not being zero width 2024-09-25 16:28:41 +01:00
George Rennie e105cae4a9 opt_demorgan: add test for zero width cell 2024-09-25 16:10:16 +01:00
Martin Povišer ea765686b6 aiger2: Adjust hierarchy/port handling 2024-09-18 16:55:02 +02:00
Martin Povišer 6c1fa45995 aiger2: Ingest `$pmux` 2024-09-18 16:42:56 +02:00
Martin Povišer d5756eb9be tests: Add trivial liberty -unit_delay test 2024-09-18 16:17:03 +02:00
Martin Povišer 31476e89b6 tests: Avoid temporary script file 2024-09-18 16:17:03 +02:00
Martin Povišer 8e29675a23 aiger2: Support `$bwmux`, comparison operators 2024-09-17 13:55:58 +02:00
Martin Povišer fb26945a20 Start an 'aiger2' backend 2024-09-17 13:55:58 +02:00
Martin Povišer 4cfdb7ab50 Adjust operation naming in aigmap test 2024-09-17 13:55:58 +02:00
Emil J 52382c6544
Merge pull request #4583 from YosysHQ/emil/clock_gate 
clockgate: centralize clock enables out of FFs
 2024-09-16 15:41:01 +02:00
N. Engelhardt c8b42b7d48
Merge pull request #4538 from RCoeurjoly/verific_bounds 2024-09-12 13:04:04 +02:00
Emil J. Tywoniak 1e999a3cb7 clockgate: EN can be a bit on a multi-bit wire 2024-09-11 19:18:25 +02:00
Roland Coeurjoly bdc43c6592 Add left and right bound properties to wire. Add test. Fix printing 
for signed attributes

Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-09-10 12:52:42 +02:00
Emil J. Tywoniak 7e473299bd clockgate: bail on constant signals 2024-09-09 21:20:19 +02:00
Emil J. Tywoniak dc039d8be4 clockgate: test fine-grained cells 2024-09-09 21:03:22 +02:00
Emil J. Tywoniak e64fceef70 clockgate: prototype clock gating 2024-09-09 15:00:54 +02:00
Miodrag Milanović b20df72e1e
Merge pull request #4536 from YosysHQ/functional 
Functional Backend
 2024-09-06 10:05:04 +02:00
Emily Schmidt 5a476a8d29 functional tests: run from make tests but not smtlib/rkt tests 2024-09-04 10:30:08 +01:00
Krystine Sherwin 7fe9157df2 smtr: Add rkt to functional tests 2024-09-03 11:32:02 +01:00
Miodrag Milanović 598d010349
Merge pull request #4504 from YosysHQ/nanoxplore 
NanoXplore synthesis
 2024-09-03 10:19:44 +02:00
Emily Schmidt 2b8db94aa0 functional backend: add test to verify test_generic 2024-08-29 13:14:18 +01:00
George Rennie 8206951f77 proc_dff: add tests 2024-08-28 16:24:47 +01:00
Emily Schmidt 761eff594f functional backend: missing includes for stl containers 2024-08-22 11:13:58 +01:00
Roland Coeurjoly 91e3773b51 Ensure signed constants are correctly parsed, represented, and exported in RTLIL. Add a test to check parsing and exporting 2024-08-21 14:28:42 +01:00
Emily Schmidt 831da51255 add picorv test to functional backend 2024-08-21 11:04:11 +01:00
Emily Schmidt 99effb6789 add support for initializing registers and memories to the functional backend 2024-08-21 11:03:29 +01:00
Emily Schmidt 145af6f10d fix memory handling in functional backend, add more error messages and comments for memory edgecases 2024-08-21 11:03:29 +01:00
Emily Schmidt 3cd5f4ed83 add support for RTLIL cells with multiple outputs to the functional backend, implement $fa,$lcu,$alu 2024-08-21 11:03:29 +01:00
Emily Schmidt c0c90c2c31 functional backend: require shift width == clog2(operand width) 2024-08-21 11:03:29 +01:00
Emily Schmidt 6922633b0b fix a few bugs in the functional backend and refactor the testing 2024-08-21 11:03:29 +01:00
Emily Schmidt 674e6d201d rewrite functional backend test code in python 2024-08-21 11:03:29 +01:00
Roland Coeurjoly 80582ed3af Check the existance of a different set of outputs. No need for (push 1) nor (pop 1) 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 7cff8fa3a3 Fix corner case of pos cell with input and output being same width 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 5780357cd9 Emit valid SMT for stateful designs, fix some cells 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 50f487e08c Added $ff test 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 762f8dd822 Add readme explaining how to create test files 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 73ed514623 Check that there are not other solutions other than the first given 2024-08-21 11:02:31 +01:00
Roland Coeurjoly cb5f08364c ´SMT success only if simulation is equivalent 2024-08-21 11:02:31 +01:00
Roland Coeurjoly e235fc704d Create std::mt19937 only once 2024-08-21 11:02:31 +01:00
Emily Schmidt 21bb1cf1bc rewrite functional c++ simulation library 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 39bf4f04f7 Create VCD file from SMT file 2024-08-21 11:02:31 +01:00
Roland Coeurjoly b98210d8ac Valid SMT is emitted, improved test script 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 71aaa1c80d Consolidate tests scripts into one 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 547c5466ec Ignore smt2 files, generated by the execution of the tests 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 54225b5c42 Add test for SMT backend. Tests if SMT is valid and compares simulation with yosys sim 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 720429b1fd Add test_cell tests for C++ functional backend 2024-08-21 11:01:09 +01:00
Emil J e0d3bbf3c3
Merge pull request #4452 from phsauter/shiftadd-underflow-fix 
peepopt: avoid shift-amount underflow
 2024-08-19 15:45:46 +02:00
Miodrag Milanovic 54d237ff82 add min_ce_use and min_srst_use parameters 2024-08-15 17:50:36 +02:00
Miodrag Milanovic dbf1d037e8 Cleanup 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 3848563600 Update tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 1a6e5c671f Add meminit handling for NX_RFB_U 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 40f05009e3 Fix CY chaining and CI injection 2024-08-15 17:50:36 +02:00
Miodrag Milanovic f4d8ea4c40 Start adding RFB simulation models 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 7e4aef06e4 Add register file mapping 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 41ae513d60 support other I/O configurations 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 34f08bc639 Enable nanoxplore tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic a5bfb23b47 start cleaning rams 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 65d2ebac9d fix test 2024-08-15 17:50:36 +02:00
Lofty b0c4add642 Added lutram 2024-08-15 17:50:36 +02:00
Lofty b3f59c9820 Add NX_CY 2024-08-15 17:50:36 +02:00
Lofty b4e9bb0d85 Add FFs and related tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic b4a17cccc3 add few more tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 93543bd874 add lut tests 2024-08-15 17:50:36 +02:00
Martin Povišer c35f5e379c Extend liberty tests 2024-08-13 18:47:36 +02:00
George Rennie b6ceff2aab peepopt clockgateff: add testcase 2024-08-07 10:21:52 +01:00
N. Engelhardt 9f869b265c
Merge pull request #4474 from tony-min-1/mchp 
Add PolarFire FPGA support
 2024-07-29 15:28:44 +02:00
Emil J. Tywoniak 01fd72520f proc_rom: test src attribute on memories 2024-07-29 10:13:45 +02:00
chunlin min 3db69b7a10 inline all tests. Add switch to remove init values as PolarFire DFFs do not support init 2024-07-08 17:03:03 -04:00
Tony Min d41688f7d7
Revisions (#4) 
* area should be 1 for all LUTs

* clean up macros

* add log_assert to fail noisily when encountering oddly configured DFF

* clean help msg

* flatten set to true by default

* update

* merge mult tests

* remove redundant test

* move all dsp tests to single file and remove redundant tests

* update ram tests

* add more dff tests

* fix c++20 compile errors

* add option to dump verilog

* default to use abc9

* remove -abc9 option since its the default now

---------

Co-authored-by: tony <minchunlin@gmail.com>
 2024-07-08 10:57:16 -04:00
Tony Min 6fe0e00050
Add missing u sram init (#3) 
add missing INIT for uSRAM
 2024-07-04 16:39:10 -04:00
chunlin min 8e7ec2d660 add assertions for synth_microchip tests 2024-07-04 15:45:44 -04:00
chunlin min e3c4791e5b move microchip tests from techlibs/microchip/tests to tests/arch/microchip 2024-07-04 14:16:52 -04:00
phsauter 34b5c6d062 peepopt: avoid shift-amount underflow 2024-06-13 23:30:07 +02:00
Marian Buschsieweke 7f89a45ad7 cxxxrtl: fix use of format specifiers in test 
This fix a few instances of incorrect (and non-portable) use of format
specifiers.
 2024-06-11 07:22:39 +01:00