356 Commits

Author	SHA1	Message	Date
Udi Finkelstein	73d426bc87	Modified errors into warnings ... No longer false warnings for memories and assertions	2018-06-05 18:03:22 +03:00
Udi Finkelstein	80d9d15f1c	reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files	2018-06-05 18:00:06 +03:00
Clifford Wolf	724cead61d	Added "pmuxtree" command	2015-04-07 20:27:10 +02:00
Clifford Wolf	01ef34c147	Added tests/various/constmsk_test.ys	2014-09-04 15:07:30 +02:00
Clifford Wolf	d49dec1f86	Added tests/various/.gitignore	2014-07-26 17:43:41 +02:00
Clifford Wolf	b21ebe1859	Added tests/various/submod_extract.ys	2014-07-26 17:22:18 +02:00