5 Commits

Author	SHA1	Message	Date
Charlotte	7f7c61c9f0	fmt: remove lzero by lowering during Verilog parse ... See https://github.com/YosysHQ/yosys/pull/3721#issuecomment-1502037466 -- this reduces logic within the cell, and makes the rules that apply much more clear.	2023-08-11 04:46:52 +02:00
Charlotte	c382d7d3ac	fmt: %t/$time support	2023-08-11 04:46:52 +02:00
Charlotte	b0f69f2cd5	tests: test cxxrtl against iverilog (and uncover bug!)	2023-08-11 04:46:52 +02:00
Charlotte	095b093f4a	cxxrtl: first pass of $print impl	2023-08-11 04:46:52 +02:00
whitequark	9ea241711e	kernel: add format string helpers, `fmt`.	2023-08-11 04:46:52 +02:00