Commit Graph

640 Commits

Author SHA1 Message Date
Martin Povišer 61abca10a3 passes: show: Touch chunk iteration in gen_portbox
Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
Martin Povišer 60318a5cd8 passes: show: Label no_signode flag
Label the flag and rearrange the control flow a bit.

Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
Martin Povišer 8b1f5fba62 passes: show: Simplify wire bit range logic
Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
Martin Povišer ad149cc42a passes: show: Factor out 'join_label_pieces'
In two places, we are joining label pieces by a '|' separator. We go
about it by putting the separator behind each entry, then removing the
trailing separator in a final fixup pass on the built string. For easier
reading, replace those occurrences by a new factored-out
'join_label_pieces' function.

Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
Martin Povišer 5848790835 passes: show: Label signed_suffix flag
To make it easier to follow what's going on.

Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
Martin Povišer 13700e12e5 passes: show: s/idx/dot_idx/ for readability
Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
Martin Povišer e3709ce776 passes: show: Fix portbox bit ranges in case of driven signals
When the 'show' pass generates portboxes to detail the connection of
cell ports to wires, it has special handling of signal chunk
repetitions, but those repetitions are not accounted for in the
displayed bit range in case of cell outputs. Fix that, and so bring it
into consistence with the behavior on cell inputs.

So, taking for example the following Verilog snippet,

  module DRIVER (Q);
     output [7:0] Q;
     assign Q = 8'b10101010;
  endmodule

  module main;
     wire w;
     DRIVER driver(.Q({8{w}}));
  endmodule

make the show pass display '7:0 - 8x 0:0' in the driver-to-w portbox
instead of '7:7 - 8x 0:0' which it displayed formerly.

Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
Jannis Harder 5042600c0d xprop, setundef: Mark xprop decoding bwmuxes, exclude them from setundef
This adds the xprop_decoder attribute to bwmuxes that drive the original
unencoded signals. Setundef is changed to ignore the x inputs of these
bwmuxes, so that they survive the prep script of SBY's formal flow. This
is required to make simulation (via sim) using the prep model show the
decoded x signals instead of 0/1 values made up by the solver.
2023-01-11 18:07:16 +01:00
N. Engelhardt 4173daa708
Merge pull request #3605 from gadfort/stat-json-area 2023-01-11 16:41:44 +01:00
Claire Xen 843f329b96
Merge branch 'master' into claire/eqystuff 2023-01-11 16:33:08 +01:00
Jannis Harder 5abaa59080
Merge pull request #3537 from jix/xprop
New xprop pass
2023-01-11 16:26:04 +01:00
Miodrag Milanovic 5801152779 Deprecate gcc-4.8 2023-01-11 09:54:19 +01:00
Claire Xenia Wolf 6d56d4ecfc Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuff 2023-01-11 04:10:12 +01:00
Peter Gadfort 58cca9592d stat: ensure area is included in json output
Signed-off-by: Peter Gadfort <peter.gadfort@gmail.com>
2022-12-29 21:51:46 -05:00
Jannis Harder 4a0ed35aab xprop: Improve signal splitting code
Avoid splitting output ports twice when combining -split-outputs with
-split-public and clean up the corresponding code.
2022-12-12 17:51:01 +01:00
Claire Xenia Wolf 6a6e1d8424 Improvements in "viz" pass
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-09 18:28:17 +01:00
Claire Xenia Wolf 3454bddbe2 Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuff 2022-12-08 20:06:23 +01:00
Jannis Harder 172a8e79f0 xprop: Add -split-public option 2022-12-08 20:00:01 +01:00
Claire Xenia Wolf 068031d2aa Improvements in "viz" command
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-07 16:10:58 +01:00
Claire Xenia Wolf aeba966475 Improvements in "viz" pass
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-07 12:46:49 +01:00
Claire Xenia Wolf c679b408cb Various improvements in "viz" command
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-06 16:43:01 +01:00
Claire Xenia Wolf 2895a66784 Bugfix in splitcells pass
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-06 16:00:48 +01:00
Claire Xenia Wolf e151e44caa Improvements in "viz" command
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-04 19:32:31 +01:00
Claire Xenia Wolf c9f4b06cb2 Add "viz" pass for visualizing big-picture data flow in larger designs
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-04 11:35:10 +01:00
Claire Xenia Wolf 92fc6cd4a9 Add splitcells pass
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-04 01:33:04 +01:00
Jannis Harder 7036a312bf stat: Fix JSON output for empty designs 2022-12-02 14:36:19 +01:00
Jannis Harder ed02d52f30 tee: Allow logging command output to a given scratchpad value 2022-12-02 14:36:19 +01:00
Jannis Harder ce708122a5 New xprop pass to encode 3-valued x-propagation using 2-valued logic 2022-11-30 19:01:28 +01:00
KrystalDelusion a14dec79eb
Rst docs conversion (#3496)
Rst docs conversion
2022-11-15 12:55:22 +01:00
Kamyar Mohajerani 69787f1906 remove extra space in formating 2022-09-22 15:46:36 +01:00
Kamyar Mohajerani bc1e579483 stat: add tech tech-specific utilizations to json
- refactor resource util. estimation/calculations for Xilinx and CMOS
 - don't print log_header if "-json" is set
2022-09-22 15:46:36 +01:00
N. Engelhardt 7d35003c16
Merge pull request #3449 from YosysHQ/aki/show_pathrw 2022-08-25 17:06:29 +02:00
KrystalDelusion 9465b2af95 Fitting help messages to 80 character width
Uses the regex below to search (using vscode):
	^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\);

Finds any log messages double indented (which help messages are)
and checks if *either* there are is no newline character at the end,
*or* the number of characters before the newline is more than 80.
2022-08-24 10:40:57 +12:00
Aki Van Ness 1433a63165
yosys: passes: cmds: show: added filename re-writing to `show -lib` 2022-08-22 06:04:54 -04:00
Jannis Harder 65145db7e7 rename: Add -witness mode 2022-08-16 13:37:30 +02:00
Jannis Harder 0cdb14df41 setundef: Do not add anyseq / anyconst to unused memory port clocks
Instead set those unused clocks to zero.
2022-08-16 13:37:30 +02:00
Jannis Harder c0063288d6 Add the $anyinit cell and the formalff pass
These can be used to protect undefined flip-flop initialization values
from optimizations that are not sound for formal verification and can
help mapping all solver-provided values in witness traces for flows that
use different backends simultaneously.
2022-08-16 13:37:30 +02:00
N. Engelhardt 6f439dc59a
Merge pull request #3425 from YosysHQ/lofty/stat-json 2022-08-11 17:00:54 +02:00
Lofty 59facfa98c stat: add option for machine-readable json output 2022-08-11 13:41:01 +01:00
Lofty a48dcd1d40 rename: add -scramble-name option to randomly rename selections 2022-08-08 16:03:28 +01:00
George Rennie 5dfad5101d chformal: Rename -coverprecond to -coverenable 2022-06-18 18:28:12 +01:00
Jannis Harder e39c422734 chformal: Test -coverprecond and reuse the src attribute 2022-06-18 18:19:26 +01:00
George Rennie c659bd1878 chformal: Add -coverprecond option
This inserts $cover cells to cover the enable signal (precondition)
for the selected formal cells.
2022-06-18 18:19:26 +01:00
N. Engelhardt 3eaa9e38e0
Merge pull request #3196 from bfg86/bfg86/rename
Add -suffix option to rename -wire
2022-06-13 16:00:04 +02:00
bfg86 aedd3b7999 Updating help-text with nakengelhardts suggestion. 2022-06-13 09:35:10 +02:00
N. Engelhardt b8ede6162b
Merge pull request #3349 from nakengelhardt/select_count_scratchpad
Make 'stat' and 'select -count' save counts to scratchpad
2022-06-09 17:15:02 +02:00
Lofty aae2c01326 sta: warn on unrecognised cells only once 2022-06-08 09:31:49 +01:00
Miodrag Milanovic d88a5d26b7 Fix preventing show crashing with newer graphviz 2022-06-03 08:38:16 +02:00
N. Engelhardt 61b05051e1 also make 'stat' save counts to scratchpad 2022-06-01 16:01:07 +02:00
N. Engelhardt a55c3db384 have 'select -count' save the count to scratchpad entry 'select.count' 2022-06-01 14:39:33 +02:00
Jannis Harder fc65ea47df select: Fix -assert-none and -assert-any error output and docs
Both of these options consider a selection containing only empty modules
as non-empty. This wasn't mentioned in the documentation nor did the
error message when using `select -assert-none` list those empty modules,
which produced a very confusing error message complaining about a
non-empty selection followed by an empty listing of the selection.

This fixes the documentation and changes the `-assert-none` and
`-assert-any` assertion error messages to also output fully selected
modules (this includes selected empty modules).

It doesn't change the messages for `-assert-count` etc. as they don't
count modules.
2022-05-19 14:07:34 +02:00
Marcelina Kościelnicka 0aec79a0da show: Fix width labels.
See #3266.
2022-04-04 22:48:09 +02:00
Claire Xen e016518866
Merge pull request #2019 from boqwxp/glift
Add `glift` command for creating gate-level information flow tracking models and optimization problems
2022-02-11 15:51:24 +01:00
bfg86 7ac98d1c87 Add -suffix option to rename -wire.
See #3195
2022-02-11 00:05:13 +01:00
Marcelina Kościelnicka 93508d58da Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
Catherine 4f1d62d9b2 bugpoint: avoid infinite loop between -connections and -wires.
Fixes #3113.
2021-12-15 08:17:02 +00:00
Marcelina Kościelnicka 0aad88a2fb Add clean_zerowidth pass, use it for Verilog output.
This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.

See #3103.
2021-12-12 19:56:50 +01:00
Lofty 77327b2544 sta: very crude static timing analysis pass
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2021-11-25 17:20:27 +01:00
Marcelina Kościelnicka 107aad2cd2 show: Fix wire bit indexing.
Fixes #3078.
2021-11-12 15:09:58 +01:00
Marcelina Kościelnicka e7d89e653c Hook up $aldff support in various passes. 2021-10-02 21:01:21 +02:00
Marcelina Kościelnicka c58ac63c97 logger: Add -check-expected subcommand.
This allows us to have multiple "expect this warning" calls in a single
long script, covering only as many passes as necessary.
2021-08-12 17:41:39 +02:00
Marcelina Kościelnicka fd79217763 Add v2 memory cells. 2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka 009940f56c rtlil: Make Process handling more uniform with Cell and Wire.
- add a backlink to module from Process
- make constructor and destructor protected, expose Module functions
  to add and remove processes
2021-07-12 00:47:34 +02:00
Claire Xen 55e8f5061a
Merge pull request #2817 from YosysHQ/claire/fixemails
Fixing old e-mail addresses and deadnames
2021-06-09 13:22:52 +02:00
Zachary Snow d9f11bb7a6 autoname: simple perf optimizations 2021-06-08 15:02:42 -04:00
Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
2021-06-08 00:39:36 +02:00
Marcelina Kościelnicka c4cc888b2c kernel/rtlil: Extract some helpers for checking memory cell types.
There will soon be more (versioned) memory cells, so handle passes that
only care if a cell is memory-related by a simple helper call instead of
a hardcoded list.
2021-05-22 21:43:00 +02:00
Marcelina Kościelnicka a6081b46ce connect: Add -assert option, fix non-working sigmap.
Should be useful for writing tests.
2021-05-08 15:49:41 +02:00
Iris Johnson 4c39189b13
Clarify bugpoint documentation regarding output
Bugpoint's current documentation does specify that the result of a run is stored as the current design,
however it's easy to skim over what that means in practice. 

Add a documentation comment to explain specifically that an after bugpoint `write_xyz` pass is required to save
the reduced design.
2021-03-24 16:24:33 -05:00
Zachary Snow c8b45a4a82 bugpoint: add runner option 2021-03-17 15:54:00 -04:00
gatecat dd6d34f461 blackbox: Include whiteboxed modules
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 13:58:04 +00:00
Marcelina Kościelnicka 4e03865d5b Add support for memory writes in processes. 2021-03-08 20:16:29 +01:00
Dan Ravensloft 74dad5afe7 scc: Add -specify option to find loops in boxes 2021-01-26 16:23:08 +00:00
umarcor e61b107072 plugin: enhance no-plugin error 2020-12-29 05:50:04 +01:00
whitequark 1838edf35c bugpoint: add -wires option. 2020-12-07 09:24:35 +00:00
whitequark 2b474a01e1 bugpoint: try to remove whole processes first. 2020-12-07 08:42:54 +00:00
whitequark b1135a88dd bugpoint: accept quoted strings in -grep. 2020-12-07 08:42:54 +00:00
whitequark 75f9e9cb45 bugpoint: add -command option. 2020-12-07 08:42:54 +00:00
whitequark d6a93b8b90 check: add support for processes. 2020-11-03 15:36:27 +00:00
whitequark 191406f930 check: reformat log/help text to match most other passes 2020-11-03 12:37:02 +00:00
N. Engelhardt 3238190797 use the new isPublic() in a few places 2020-09-14 12:43:18 +02:00
whitequark 00e7dec7f5 Replace "ILANG" with "RTLIL" everywhere.
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.

Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
2020-08-26 17:29:32 +00:00
Alberto Gonzalez bbfa2d65fa
glift: Use ID() rather than string literals. 2020-07-01 19:51:48 +00:00
Alberto Gonzalez eda1af73c4
glift: Use worker pattern. 2020-07-01 19:51:47 +00:00
Alberto Gonzalez 3eb2593876
glift: Add support for $_NAND_ and $_NOR_ cells. 2020-07-01 19:51:47 +00:00
Alberto Gonzalez 8cb1a86c23
glift: Add support for $_MUX_ and $_NMUX_ cells. 2020-07-01 19:51:47 +00:00
Alberto Gonzalez 23defc6fe9
glift: Add support for $_XOR_ and $_XNOR_ cells. 2020-07-01 19:51:47 +00:00
Alberto Gonzalez 209a123b97
glift: Add initial hierarchy support. 2020-07-01 19:51:47 +00:00
Alberto Gonzalez 20ad371724
glift: Replace `YS_OVERRIDE` with `override`. 2020-07-01 19:51:47 +00:00
Alberto Gonzalez 91c20fca72
glift: Add `-simple-cost-model` option
Rather than assigning specific weights to specific versions of taint tracking logic and summing the weights of all GLIFT cells, sum the following values for each GLIFT cell:
  - 0 if the associated hole/$anyconst cell value is non-zero, i.e. reduced-precision taint tracking logic is chosen at this cell
  - 1 if the associated hole/$anyconst cell value is zero, i.e. the full-precision taint tracking logic is chosen at this cell

This simplified cost modeling reduces the potential for the QBF-SAT solver to minimize taint tracking logic area but significantly simplifies the QBF-SAT problem.
2020-07-01 19:51:47 +00:00
Alberto Gonzalez 26bd686259
glift: Add `-instrument-more` option to add 4 more versions of taint tracking logic. Also refactor a bit and update help text. 2020-07-01 19:51:46 +00:00
Alberto Gonzalez bc207d5426
glift: Change command names to better represent their functions. 2020-07-01 19:51:46 +00:00
Alberto Gonzalez ddfb9f08e2
glift: Add `-create-imprecise` command, rename other commands, and re-work the help text. 2020-07-01 19:51:46 +00:00
Alberto Gonzalez 72cebef279
glift: Add replacement scoring and area minimization option. 2020-07-01 19:51:46 +00:00
Alberto Gonzalez c36440a7ee
glift: Remove outputs by default; add `-keep-outputs` option; properly reset internal state between calls. 2020-07-01 19:51:46 +00:00
Alberto Gonzalez 19dafcd4f1
glift: Initial implementation of the `-sketchify` option. 2020-07-01 19:51:46 +00:00
Alberto Gonzalez 09848b3b9f
glift: Initial implementation of GLIFT model construction. 2020-07-01 19:51:45 +00:00
Alberto Gonzalez 5f45fe51ea
glift: Add skeleton for `glift` command. 2020-07-01 19:51:45 +00:00
Marcelina Kościelnicka b0bee396a8 Add new builtin FF types
The new types include:

- FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`)
- FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`)
- FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`)
- FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`)
- FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`)
- latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`)

The new FF types are not actually used anywhere yet (this is left
for future commits).
2020-06-23 15:40:02 +02:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Alberto Gonzalez f5d7cd60f5
splitnets: Clean up pseudo-private member usage 2020-06-13 05:47:55 +00:00
Alberto Gonzalez b70de98bd1
splitnets: Slightly improve efficiency by avoiding some unnecessary lookups 2020-06-13 05:26:30 +00:00
whitequark 2139a5c21a splitnets: propagate (*hdlname*) and disambiguate via start_offset.
This allows reliably coalescing the split wires later.
2020-06-10 19:59:08 +00:00
clairexen 369dcb4e82
Merge pull request #2085 from rswarbrick/select
Silence warning in select.cc and pass some more args by ref
2020-06-08 15:55:52 +02:00
Eddie Hung fe273faad1
Merge pull request #2081 from YosysHQ/eddie/blackbox_ast
blackbox: use Module::makeblackbox() method
2020-05-30 08:59:20 -07:00
Xiretza edd8ff2c07
Add flooring division operator
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.

This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
2020-05-28 22:59:04 +02:00
Xiretza 17163cf43a
Add flooring modulo operator
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).

This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
2020-05-28 22:59:03 +02:00
Alberto Gonzalez 5896ffd56f
printattrs: Simplify `get_indent_str()`.
Co-Authored-By: Xiretza <xiretza@xiretza.xyz>
2020-05-28 05:34:28 +00:00
Alberto Gonzalez f671c99cb8
printattrs: Refactor indentation string building for clarity.
Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-05-27 23:15:07 +00:00
Rupert Swarbrick d681c9df85 Pass some more args by reference in select.cc
Before this patch, the code passed around std::string objects by
value. It's probably not a hot-spot, but it can't hurt to avoid the
copying.

Removing the copy and clean-up code means the resulting code is ~6.1kb
smaller when compiled with GCC 9.3 and standard settings.
2020-05-27 09:42:23 +01:00
Rupert Swarbrick 061d1f0c07 Minor optimisations in select.cc's match_ids function
- Pass a string argument by reference

  - Avoid multiple calls to IdString::str and IdString::c_str

  - Avoid combining checks for size > 0 and first char (C strings are
    null terminated, so foo[0] != '\0' implies that foo has positive
    length)
2020-05-27 09:36:33 +01:00
Rupert Swarbrick 0d9beb5b2e Silence warning in select.cc
With GCC 9.3, at least, compiling select.cc spits out a warning about
an implausible bound being passed to strncmp. This comes from inlining
IdString::compare(): it turns out that passing std::string::npos as a
bound to strncmp triggers it.

This patch replaces the compare call with a memcmp with the same
effect. The repeated calls to IdString::c_str are slightly
inefficient, but I'll address that in a follow-up commit.
2020-05-27 09:34:15 +01:00
Alberto Gonzalez e50e4ee285
printattrs: Use `flags` to pretty-print the `RTLIL::Const` appropriately.
Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-05-27 08:00:00 +00:00
Alberto Gonzalez b8365547e9
misc: Add `printattrs` command. 2020-05-27 08:00:00 +00:00
Eddie Hung 721283ac2a blackbox: re-use existing Module::makeblackbox() method 2020-05-25 10:53:49 -07:00
Alberto Gonzalez 8297afe925
log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique. 2020-05-15 00:55:32 +00:00
Eddie Hung 425867d175 logger: clean up doc 2020-05-14 10:38:31 -07:00
Eddie Hung 65395168a0 logger: fix for multiple calls with same pattern 2020-05-14 10:32:07 -07:00
whitequark b43c282e4e Add WASI platform support.
This includes the following significant changes:
  * Patching ezsat and minisat to disable resource limiting code
    on WASM/WASI, since the POSIX functions they use are unavailable.
  * Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform
    does not support spawning subprocesses (i.e. Emscripten or WASI).
    This definition hides the definition of `run_command()`.
  * Adding a new Makefile flag, DISABLE_SPAWN, present in the same
    condition. This flag disables all passes that require spawning
    subprocesses for their function.
2020-04-30 18:56:25 +00:00
Eddie Hung 56dd036b97 bugpoint: improve messaging 2020-04-24 13:41:19 -07:00
Eddie Hung e602184856 bugpoint: (* keep *) to (* bugpoint_keep *); also apply to modules/cells 2020-04-24 13:26:04 -07:00
Eddie Hung 4bfe6ebea9 bugpoint: skip ports with (* keep *) on; add header 2020-04-24 11:17:09 -07:00
Eddie Hung bf021a0e1f bugpoint: improve help text 2020-04-23 12:16:55 -07:00
Eddie Hung fa9df06c9d
Merge pull request #1949 from YosysHQ/eddie/select_blackbox
select: do not select inside black-/white- boxes unless '=' prefix used
2020-04-22 15:35:05 -07:00
Claire Wolf beb9e4b299
Update passes/cmds/select.cc
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-04-22 21:31:32 +02:00
Eddie Hung eaa5a3e786 select: do not select black/white boxes by default, '=' prefix to do so 2020-04-22 10:15:56 -07:00
Eddie Hung 28623f19ee
Merge pull request #1950 from YosysHQ/eddie/design_import
design: -import to not count black/white-boxes as candidates for top
2020-04-22 09:32:13 -07:00
Marcelina Kościelnicka cd82afb740 bugpoint: Don't remove modules or cells while iterating over them.
Reported by @ZirconiumX.
2020-04-22 00:09:01 +02:00
Claire Wolf d834cc7afb Add '=' selection pattern prefix for non-blackbox only patterns
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-21 14:23:24 +02:00
whitequark f2064c8131
Merge pull request #1888 from boqwxp/cleanup_scatter
Clean up `passes/cmds/scatter.cc`.
2020-04-17 02:21:23 +00:00
whitequark 5c428996a9
Merge pull request #1882 from boqwxp/cleanup_rename
Clean up pseudo-private member usage in `passes/cmds/rename.cc`.
2020-04-17 02:20:54 +00:00
Eddie Hung dac5adde12 design: -import to not count black/white-boxes as candidates for top 2020-04-16 12:46:07 -07:00
Eddie Hung 47c8ee7fe4 select: do not select inside blackboxes 2020-04-16 12:23:34 -07:00
Alberto Gonzalez 2e3647f567
Use `dict` instead of `std::map`.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-04-16 18:56:50 +00:00
Alberto Gonzalez b94f38295a
Revert to `stringf()` rather than stringstreams. 2020-04-16 18:56:50 +00:00
Alberto Gonzalez 6081c1bbd3
Clean up pseudo-private member usage in `passes/cmds/rename.cc`. 2020-04-16 18:56:50 +00:00
Alberto Gonzalez ff8be2364e
Replace `std::map` with `dict`.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-04-16 18:49:55 +00:00
Alberto Gonzalez 0424555702
Replace pseudo-private member access to `connections_` in `passes/cmds/scatter.cc`.
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
2020-04-16 18:49:55 +00:00
Alberto Gonzalez 0787af947f
Clean up `passes/cmds/scatter.cc`. 2020-04-16 18:49:55 +00:00
Eddie Hung 254d38ca67 select: add select -unset option 2020-04-16 10:51:58 -07:00
Eddie Hung 8d3f6d0d79
Merge pull request #1928 from YosysHQ/eddie/design_delete
kernel: add design -delete option
2020-04-16 10:51:09 -07:00
Eddie Hung aa552cefa3
Merge pull request #1927 from YosysHQ/eddie/design_remove_assert
kernel: Design::remove(RTLIL::Module *) to check refcount_modules_
2020-04-16 08:06:12 -07:00
Eddie Hung a9ec0defb9 kernel: add design -delete option 2020-04-16 08:05:18 -07:00
Marcelina Kościelnicka d7da491002 setundef: Improve error messages.
Fixes #1092.
2020-04-15 16:13:28 +02:00
Eddie Hung 75bb2c8c24 design: do not delete when iterating over Design::modules() directly 2020-04-14 10:43:05 -07:00
Marcelina Kościelnicka 516857f3ba [NFCI] Deduplicate builtin FF cell types list
A few passes included the same list of FF cell types.  Make it a global
const instead.

The zinit pass also seems to include a list like that, but given that
it seems to be completely broken at the time (see #1568 discussion),
I'm going to pretend I didn't see that.
2020-04-09 18:05:06 +02:00
whitequark 42e7e44207
Merge pull request #1857 from whitequark/splitnets-skip-processes
splitnets: skip modules with processes
2020-04-09 04:03:30 +00:00
Alberto Gonzalez 64a5936bd7
Clean up `passes/cmds/connect.cc`. 2020-04-08 22:11:06 +00:00
whitequark b350398c04
Merge pull request #1874 from boqwxp/cleanup_show
Clean up `passes/cmds/show.cc`.
2020-04-06 18:32:20 +00:00
Alberto Gonzalez f4346a0400
Use more descriptive variable name.
Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-04-06 14:48:27 +00:00